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News and Articles News Releases | Published Articles News Releases Synopsys Delivers 45-Nanometer Low Power Reference Flow for Common Platform Technology Validated with ARM Physical IP 2. Synopsys and UMC Release 65-Nanometer Low Power Design Flow Enabled by the Unified Power Format Oticon Tapes Out Innovative Hearing-Aid DSP Using Synopsys IC Compiler Synopsys and SMIC Deliver Enhanced 90-Nanometer Reference Flow to Reduce IC Design and Test Costs Synopsys and UMC Deliver 65-Nanometer Reference Flow Dubai Silicon Oasis Chooses Synopsys to Establish First IC Design Center in the United Arab Emirates July 9, 2007 Synopsys Tools, IP and Services Enable First-Silicon Success for Teradici's Complex SoC Synopsys Announces Advanced Techniques In TSMC Reference Flow 8.0 to Address 45nm Design Challenges June 12, 2007 Flow Includes Statistical Timing Analysis for Intra-die Variation, Automated DFM Hot-spot Fixing and New Dynamic Low-power Design Methodologies Synopsys' Reference Flow For Common Platform Technology Wins Prestigious IBM Beacon Award April 5, 2007 Complete 65-Nanometer Design Flow Recognized as Common Platform Technology Critical Success Factor Synopsys IC Compiler Enables Fully Automated 65-Nanometer Implementation Flow for ARM Cortex-A8 Processor March 28, 2007 Flow Delivers a 5-10X Boost in Productivity for Mobile and Consumer Applications Synopsys Enables STMicroelectronics to Achieve First-Silicon Success for 65-nm Dual High-Definition MPEG-4 Decoder March 27, 2007 Comprehensive Implementation, System-Level and Verification Solutions Speed Time-to-Market for STi7200 Dual-Video-Stream Device Synopsys Named IBM-Authorized Power Architecture Design Center January 29, 2007 Synopsys to Directly License Foundry-Portable PowerPC Cores Synopsys and UMC Enhance 90-nm Reference Flow with Advanced Low Power and Design for Test January 9, 2007 Synopsys' Galaxy Design Platform Validated with Multi-Vdd Capability for UMC's 90-nm Process Hua Hong NEC and Synopsys Jointly Develop Reference Design Flow 2.0 October 13, 2006 Hua Hong NEC Chooses Synopsys as Primary EDA Provider SMIC and Synopsys Deliver Reference Design Flow 3.0 for 90-Nanometer Designs September 05, 2006 Reference Design Flow Features New Low Power and DFM Capabilities Based on Synopsys' Galaxy™ Design and Discovery™ Verification Platforms Synopsys Delivers First 65-NM Reference Flow for IBM, Samsung and Chartered July 19, 2006 Common Platform Technology Reference Flow Adds Critical Area Design-for-Manufacturing Capability in IC Compiler TSMC Reference Flow 7.0 Incorporates Synopsys' IC Compiler July 18, 2006 Reference Flow 7.0 Incorporates Latest Technologies for Low Power and Yield Optimization to Address 65-nanometer Design Challenges Synopsys' IC Compiler Completes Tapeout of High-Density Sunplus Consumer Design June 29, 2006 Sunplus Selects Synopsys Professional Services to Achieve Aggressive Schedule and Cost Goals Design Compiler Topographical Technology-Based ARM-Synopsys Reference Methodology Delivers Higher Productivity May 15, 2006 Enhanced Methodology Accelerates Time-to-Market for ARM Processors, Including Next-generation ARM Cortex-R4 Processor Synopsys Introduces Pilot Design Environment Feb. 27, 2006 Production-Ready Environment Integrates Proven RTL-to-GDSII Flow With New Utilities to Improve Design Productivity and Tapeout Predictability Synopsys, IBM, Chartered and ARM Collaborate to Extend low-power 90nm Reference Flow Feb. 27, 2006 Flow Supports IC Compiler for Common Platform's Low-Power Process Synopsys and UMC Partner on Low Power 90-nm Reference Design Flow to Deliver Faster Time to SoC Success Nov. 21, 2005 Reference Design Flow Features Low Power Management and Design-for-Manufacturing Automation Capabilities Synopsys Design Solutions Enable Implementation and Deployment of ARM Cortex-A8 Processor to Licensees Oct 4, 2005 ARM and Synopsys Collaborate to Demonstrate Galaxy Design and Discovery Verification Flow for ARM Cortex-A8 Processor Implementation Synopsys and ARM Announce Synopsys IC Compiler Incorporated in Latest ARM-Synopsys Reference Methodology Oct 3, 2005 Enhanced Reference Methodology delivers 10 percent higher performance SMIC and Synopsys Announce Reference Design Flow 2.0 July 19, 2005 Latest Flow for 0.13-micron Process Offers Advanced Floor Planning, Signal Integrity and Reliability Features Key Synopsys Low Power and DFM Technologies Support TSMC Reference Flow 6.0 June 9, 2005 Reference flow significantly reduces the physical verification processing time from days to hours for advanced 65-nanometer (nm) and 45-nm integrated circuits Synopsys and IBM Announce Availability of Fully Synthesizable PowerPC Cores and SystemC Models June 8, 2005 Synopsys and IBM announce the availability of fully synthesizable versions of IBM's PowerPC® 405 and 440 processors as part of the DesignWare® Star IP (intellectual property) program Synopsys Provides Low-Power Reference Flow for IBM-Chartered 90-Nanometer Process Platform May 25, 2005 Complete RTL to Production-Ready GDSII Flow Speeds 90-nm Designs ARM and Synopsys Announce Industry-First and Recommended Flow for ARM11 Family with Intelligent Energy Manager Technology January 31, 2005 Synopsys' ASIC compatible design flow including DC FPGA and Formality products and Professional Services Now Supports Altera's Stratix II and HardCopy II Families Grace and Synopsys Jointly Develop Reference Design Flow
View current Synopsys News Releases Published Articles Complex SoC Testing with a Core-Based DFT Strategy SoC Design and Development Applying Constrained-Random Verification to Microprocessors Practical Ways To Estimate, Implement, And Verify SoC Decoupling Capacitance EDN: August 2007 Practical Power Network Synthesis For Power-Gating Designs EE Times: June 2007 Proper Planning Assures SoC Power Integrity ChipDesign: January 2007 A Practical Approach to Measuring IC Design Productivity Synopsys Insight: January 2007 Metrics Measure IC Design Productivity EDA Design Line: October 2006 Power Planning for SoCs Evaluate IP Timing Constraints Before Use in SOC Designs A Practical Methodology Calculates IR Drop Targets for SoCs Static Timing Analysis for Multi-Voltage Designs Consistency in Process and Measurement: Tracking Long-Term Design Productivity Gains Dual Threshold Voltages and Power-Gating Design Flows offer Good Results Pilot Design Environment Integrates Flow Synopsys Sets Pilot Design Environment to Flight Rail-Signoff Analysis Ensures SoC Power Integrity Integrating DFM in the Design Flow Success by Design Try A Hybrid Flow To Overcome Hierarchical Design Limitations Diversifying Design Trends in North America Honeywell and Synopsys: Concept-to-Parts Solutions for Next Generation Rad-Hard ASICs Front-End Signal Integrity Methods Save Back-End Repair Time Speeding-up Signal Integrity Analysis and Repair for SoCs Take Care to Avoid Signal Integrity Problems Accurate Power-Analysis Techniques Support Smart SoC Design Choices Hot Chips??.... Not! Design-Planning Guidelines Prevent Chip Surprises 'Best Practices' Improve Hierarchical Design Constraints Using Multiple Voltages to Manage Power Timing Issues in Low-Power 3G Chips Addressing System-Level Challenges in High-Speed Communication Chips WCDMA Baseband Design Faces Challenge View Professional Services Published Articles Archives |
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