• Qualify and assemble IP from multiple sources into a single chip implementation
• Rapidly integrate and optimize DesignWare® Cores into your SoC with experts in IP methodologies
• Prototype and implement ARM® and AMBA™-based subsystems

Featured Technical paper
SPIRIT-based IP Assembly and SDC promotion for a 65nm System-on-Chip using coreAssembler Sal Tiralongo, Synopsys Professional Services, Synopys Inc. Stephane Maulet, Synopsys Professional Services, Synopys Inc. Emanuele Irrera, Synopsys Professional Services, Synopys Inc. Olivier Florent, STMicroelectronics Ltd. Philip Cuney, STMicroelectronics Ltd. Cyril Vartanian, STMicroelectronics Ltd.

A common challenge in SoC design is that new RTL code for application-specific blocks has to be developed and tuned, then integrated with existing code that typically comes from multiple sources with varying degrees of quality. Achieving a high-quality RTL representation of the complete chip design is critical for ensuring the implementation will meet functional and performance requirements in a predictable manner.

As the provider of the world's most widely used IP cores and building block libraries, Synopsys is expert in the creation and integration of reusable IP blocks. Synopsys helped pioneer design reuse methodologies. In fact, we wrote the book.

Leveraging these disciplined IP development methodologies and our expertise with the DesignWare® IP portfolio, Synopsys Professional Services helps you rapidly and predictably migrate your design from RTL to GDSII. Our consultants will work with your design team to optimize the chip's micro-architecture, select and qualify IP, and then integrate the blocks into an optimized implementation. (For customers that implement proprietary subsystems in their SoCs, our expertise includes the creation of custom IP "wrappers" that interface industry-standard IP to your proprietary buses.)

Typical SoC construction with standard and proprietary IP blocks

Functional verification of the RTL design is a huge challenge, whether the RTL is new or from pre-existing IP blocks. Verifying that all design blocks are correct, both as standalone designs and in the context of the fully integrated chip, remains the number one bottleneck for chip developers. Synopsys' suite of DesignWare Verification IP (VIP) complements other Smart RTL verification techniques - such as "intelligent" testbenches that automate test generation and analysis - to provide more comprehensive coverage in a shorter amount of time.

Synopsys Professional Services also has significant expertise in implementing ARM®-based SoCs, delivering core hardening and integration services through ARM-approved design centers.

Synopsys Professional Services' IP Integration services include:

• Qualifying and optimizing existing internal and 3rd party IP blocks
• Integrating internal and 3rd-party IP blocks with DesignWare Cores and ARM processor cores
• Developing and optimizing new RTL code
• Hardening synthesizable ("soft") IP cores
• Bridging custom bus interfaces to standard IP blocks
• Tuning the chip's micro-architecture
• Prototyping and integrating AMBA-based subsystems
• Developing intelligent testbenches
• Complete RTL to GDSII SoC integration

Datasheets

• IP Integration

Related Technical Papers and Articles

• IEEE SOCC 2005
  Challenges in PowerPC440-FS Soft Core Development: Timing perspective
  Terry Biggs, Ken Umino and Kaijian Shi,Synopsys Professional Services, Synopsys Inc.
  
• SNUG Boston 2005
  AMBA DesignWare® and coreAssembler Simplify the Design Flow and Improve Design Timing for STMicroelectronics Digital Radio Controller & Audio Decoder
  Mauro Bosco, ST Microelectronics
  Sam Bordbar, Synopsys Professional Services
  Andreas Vielhaber, Synopsys, Inc
• White Paper
  Systems-On-Chip for High Speed Communication Systems
  

Related Customer Success Stories

Cray
"We didn't know such a solution was possible until we worked with Synopsys Professional Services."

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"Some skeptics at Motorola thought full-chip STA couldn't be done, given the state of the legacy IP used on the chip. Now they have complete confidence in the methodology and are propagating it to other project teams and design centers."

DMC Stratex
"We needed a partner to complement our background. The partner needed to have SoC knowledge and be capable of absorbing quickly our years of experience in the key relations,interactions and tradeoffs between the modem core, the wireless subsystem and other subsystems in the product."

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