• Upgrade your design flow to handle 65, 90 and 130 nanometer designs
• Install proven sub-flows to address VDSM effects such as signal integrity and power
• Complete, silicon-proven and deployed Pilot Design Environment to enhance productivity

Featured Technical paper
Setting Up a Versatile Flow & Environment To Improve Design Productivity Andy Potemski, Synopsys Professional Services

Today's nanometer design geometries put tremendous pressure on design teams to maintain advanced design flows to achieve any satisfactory level of predictability and productivity in the chip design process. Timing closure remains the dominant challenge, but timing is further complicated with the effects of very deep sub-micron (VDSM) processes in the form of signal integrity, power consumption, manufacturability and testability. Design flows that were stretched to their limits to produce 0.13 micron designs may not work at all at 90 or 65 nanometers without major enhancements.

Extensive experience with advanced designs, expertise with Synopsys' Galaxy™ and Discovery™ platforms, and significant investment in building and maintaining leading-edge flows in our own design centers make Synopsys Professional Services uniquely capable of helping you optimize your design flow for the challenges of implementing and verifying nanometer ASICs. And now, with the availability of the Pilot Design Environment, you can deploy a complete and tapeout-proven design system that helps you addresses both design- and project-related bottlenecks to improve your team's productivity and tapeout predictability.

Your design needs are specific; so are our services. From a production-ready design environment to specialized sub-flows that address specific VDSM issues such as power optimization, signal integrity, test and functional verification, our consultants will develop and deploy solutions proven in silicon. And since Synopsys co-developed the reference flows for many of the leading IP providers and foundries such as ARM, TSMC, IBM, Chartered, Samsung Common Platform, we are the natural choice to customize and deploy them into your production design environment.

Because we're Synopsys, we're continually monitoring new tool releases and applying their most advanced features to the design flows employed in our own IC design centers as well as at our leading customers. That enables you to take advantage of the updates and enhancements we are continuously making to our internal design environment, as well as our consultants' experience helping some of the industry's premier design organizations implement their leading-edge flows.

Whether you're at the beginning or in the middle of your design project, whether you need a minor upgrade to your flow or a complete design environment to address a new nanometer design node, Synopsys Professional Services will help you eliminate the bottlenecks that impact your design productivity.

Synopsys Professional Services' Flow Optimization services include:

• Assessment of your existing design flow and environment
• Implementing production-ready sub-flows for project-specific challenges (e.g., timing, SI, low power, design-for-test)
• Deploying complete design flows and the Pilot Design Environment to address new technology (i.e., 130nm, 90nm, 65nm) or ASIC-to-COT migrations
• Instantiating customer-specific implementation methodologies (e.g., hierarchical or "virtual flat" design)
• Incorporating new verification methods (such as assertions, functional coverage, and testbench automation) into existing environment
• Validation of new a new flow or sub-flow with a "pipe-cleaner" design and/or test chip

Related Technical Papers and Articles

• SNUG Europe 2006
  SPIRIT-based IP Assembly and SDC promotion for a 65nm System-on-Chip using coreAssembler
  Sal Tiralongo, Synopsys Professional Services, Synopys Inc.
  Stephane Maulet, Synopsys Professional Services, Synopys Inc.
  Emanuele Irrera, Synopsys Professional Services, Synopys Inc.
  Olivier Florent, STMicroelectronics Ltd.
  Philip Cuney, STMicroelectronics Ltd.
  Cyril Vartanian, STMicroelectronics Ltd
  An efficient script-based RTL-to-GDSII flow using the Jupiter-XT - PC - Astro tool chain in 130 nm on a 350K-instance design
  Pierre-Marie Signe, Abilis Systems
  John Lofgren, Synopsys Professional Services, Synopys Inc.
• Compiler
  Integrating DFM in the Design Flow
  January 2006
• White Paper
  Setting Up a Versatile Flow & Environment To Improve Design Productivity
  Andy Potemski, Synopsys Professional Services
  Measuring and Improving IC Design Productivity
  Michael Solka, Synopsys Professional Services
  Power Integrity for SoCs: Power Planning and Signoff Flows

Related Customer Success Stories

Tundra
“Our CAD team was able to deploy the Pilot Design Environment to a new site and start running the main flow steps almost immediately. Methodologies associated with designing advanced chips that take years to learn and understand were incorporated into Pilot.”

ARC International
"We were not just interested in buying new tools. We were interested in a verification flow that would work well for our customers. Synopsys Professional Services offered the best total package."

STMicroelectronics
"It would have taken us months to develop our new testing environment in-house. With Synopsys' help, it took a matter of weeks, and we have a valuable additional service to offer our customers."

Motorola
"Synopsys helped us move to a flexible synthesis-centric design process that emphasized automation, reuse and predictability."

Other Customer Success Stories

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