• Leverage tapeout-proven RTL to GDSII production flows for predictable results
• Complement your design team's competencies with experienced design specialists
• Introduce new techniques and methodologies into your design environment, such as
  optimizations for power

Getting your chips into volume production on a fast, predictable schedule becomes more and more difficult with each new process node. At geometries of 90 nm and below, the risk of a protracted design cycle - and its associated cost burden - becomes a real threat to the health of your business or product development program.

Through more than 10 years of working with our customers on their most challenging chip designs, Synopsys Professional Services has built a leading-edge design competency and infrastructure, with consultants skilled in the latest EDA technology and design practices. And we bring that knowledge and expertise to each and every customer engagement, identifying then resolving the design bottlenecks that pose the greatest risks to your project, providing support all the way through tapeout. Whether you need to outsource the entire chip design or augment your team with on-site design assistance - or a combination of the two - Synopsys Professional Services offers flexible engagement models that best address your design goals.

The extraordinary levels of integration afforded by very deep sub-micron (VDSM) processes amplify the challenges in physical design. Closing timing in a predictable manner at both the block and chip levels requires a thorough understanding of VDSM effects. Signal integrity, testability, and power issues are first order considerations, their interdependencies further complicating design closure. Specializing in RTL to GDSII design, Synopsys Professional Services knows that dealing with these and other VDSM factors early in the design flow helps ensure an optimized implementation - without any surprises.

An often-underestimated task that can have a significant impact on design quality and schedule is achieving specification closure, both at the block and chip levels. We work directly with your system architects to ensure the specifications capture design intent, helping to minimize the iterations between the architecture and RTL implementation. In fact, strategic alliances with leading manufacturing service providers enable us to deliver complete Concept-to-Parts solutions, with flexible points for design handoff.

Leveraging Synopsys' technology-leading design and verification platforms, DesignWare® IP, power optimization solutions and design flows proven in our own design centers, our consultants help you improve the quality of your design results and get your chips out the door. Our close collaboration with your design team also ensures methodology and knowledge transfer so that you are better prepared for your next round of design challenges.

Synopsys Professional Services' Design Realization services include:

• Hierarchical budgeting and design planning
• SI-aware place & route
• Full-chip timing/SI closure, static timing analysis and sign-off
• Qualifying libraries, existing RTL and design constraints
• Generating and optimizing clock trees
• Power planning and optimization
• Full-chip extraction and physical verification
• Support for netlist, placed-gates, or GDSII manufacturing handoffs
• Transferring demonstrated methods and baseline scripts for follow-on project use
• Complete turnkey design solutions with flexible handoffs, from concept to parts

• Design Realization
• Netlist to GDSII
• Concept to Parts

• SNUG San Jose 2006
  1.2 – 1.5 + M instances flat design for 0.13um process
  Steve Doan, Synopsys Inc.
  Koshi Matsushita, Synopsys Inc.
  Chien-yeh Wu, Synopsys Inc.
  Srini Burugu, Synopsys Inc.
  
• Automated FFT RTL creation using Verilog with Matlab and Perl
  Richard Hayden , Synopsys Professional Services
  Cole O’Berry, Synopsys Professional Services
  John Kuhns , Synopsys Professional Services
• SNUG Boston 2005
  Method for Data Link Layer and Physical Layer Error Insertion
  Jim Sweeten, Stargen, Inc.
  Tony Ezell, Synopsys Professional Services
• SNUG Europe 2005
  Clock Isolation Logic and Circuit for Complex SoC Designs
  Hichem Belhadj Actel Co.
  Kaijian Shi IP and Design Services, Synopsys Inc.
• White Paper
  Hierarchical Design Techniques
• Electronic Business
  Success by Design
  September 1, 2005

picoChip
"Using Synopsys tools entirely with Synopsys Professional Services was the fastest way to get this powerful architecture to silicon, and then to customers."

Leadtek
"We followed the Synopsys design flow, and the chip is passing tests without any problems. We will use Synopsys Professional Services and their RTL design methodology for our future chips."

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