IP Integration Proven Methods for Rapid Full Chip Integration

Overview
As the size of system-on-chip (SoC) designs increases, RTL designers are relying on intellectual property (IP) components when feasible in order to focus their efforts on creating new RTL for core application sub-systems. To ensure the quality of the RTL design, intelligent functional verification must be applied to guarantee true system functionality.

Synopsys Professional Services has the capability to handle the challenges of RTL design, optimization, and functional verification for even the largest SoCs. Our teams’ expertise is based on years of experience with a wide range of SoC design projects on tasks ranging from high-level concept to final GDSII tape-out. From this wide array of experience, you can choose the type of design support that best suits your requirements.

Services Throughout the Design Project
Because today’s SoCs integrate many different types of functional intellectual property (IP) and demand the use of specialized tools and methodologies, design teams must possess a multitude of design skills. Most design teams have strengths in particular areas of the design flow, so optimizing the use of those strengths in the design process is a strategy for gaining a competitive advantage. The key to successful execution is to prevent weaknesses in other areas of the flow from becoming competitive disadvantages.

Figure 1. Synopsys Professional Services offers a wide variety of design services
addressing the toughest design challenges.

That’s where Synopsys Professional Services can help—we offer services in any or all of the following areas of design:

• System-level design—Create an executable specification, then convert to RTL with complete functional verification.
• RTL design—Optimize and validate the design’s micro-architecture, evaluate RTL quality, and deploy intelligent functional verification.
• Physical design—Carry through the design from RTL to GDSII.
• Concept-to-parts service—Begin at any high level of abstraction (e.g., spec or RTL) and deliver working silicon.

For all or part of your design project, Synopsys provides services in the way that best meets your specific requirements, including design and methodology assistance and/or design outsourcing.

Figure 2. The typical SoC includes design blocks from multiple sources. Synopsys’ RTL
design services address the creation of new blocks, the qualification and integration of
existing blocks, and functional verification at the block and chip levels.

Figure 3. Synopsys leverages the DesignWare IP portfolio to assemble
AMBA-based processor subsystems.

RTL Design
RTL design services include design tasks from specification to a verified RTL description. As part of our RTL design services, we apply specialized methodologies for complex, high-performance SoCs to optimize the micro-architecture, validate the SoC’s overall architecture, evaluate RTL quality, and deploy intelligent functional verification.

The RTL flow begins with micro-architecture design and proceeds to VHDL or Verilog design (following your documented design and coding styles upon request). To facilitate design reuse, the design and coding can be verified against rule sets based on the Synopsys co-authored Reuse Methodology Manual for System-On-A-Chip Designs.

Because proven, interoperable IP is key to successful SoC design, we leverage Synopsys’ DesignWare®, portfolio of synthesizable and verification IP. This IP includes the commonly used infrastructure IP in the DesignWare Library, as well as standardsbased connectivity IP in DesignWare Cores. For other IP, an RTL quality assurance methodology reveals design issues early on. This methodology includes code purification using Synopsys’ ProVHDL and ProVerilog code checkers.

The RTL can also be optimized further to meet challenging goals for clock speed, power, or block size. For high-performance datapath design, Module Compiler™ has proven useful for optimizing clock speed and pipeline latency. Module Compiler also allows fast exploration of different datapath architectures.

For complex SoCs with tough performance requirements, Synopsys can apply systemlevel modeling to reveal architecture bottlenecks that sometimes take many RTL iterations to resolve. By capturing the functional design intent in SystemC, we can accurately size on-chip buses and validate the architecture’s ability to meet key requirements for parameters such as data throughput and latency.

Figure 4. Looking at the verification flow from the bottom up, Layer 0 connects
the testbench to the design under test (DUT) with abstracted I/O names. Layer 1
is a bus functional model that provides cycle-accurate framing and de-framing
and monitors frame validity. Layer 2 operates the DUT with real data configured
in the frames. Layer 3 rapidly creates and validates the streams needed to
test corner cases and perform stress testing. Dividing the tasks among these
layers makes it practical to reuse the testbench for a variety of applications by
changing only one or two of the layers.

Functional Verification
Since functional verification is often the largest — and still growing — portion of the total design effort, the key to saving time while ensuring high design quality is to make verification methods more intelligent and reusable. Synopsys Professional Services’ approach is to create “intelligent”, selfchecking testbenches that are reusable between block-level and system-level verification, as well as for derivative designs. Leveraging the Synopsys DesignWare Verification IP library of bus-functional models helps in this effort. Further, using constrained, random-stimulus generation to create simulation inputs helps exercise the design with high coverage. These methods give rapid results and enable the creation of new test cases quickly in response to initial coverage metrics.

Assertions inserted in context to RTL descriptions also bring great improvements to verification. Overall, assertions provide a simulation reference by communicating the design intent. More specifically, assertions used with the Synopsys VCS™ 7.0 simulator make it possible to evaluate and thus improve functional coverage.

For creating testbenches, we apply a pre-existing reference verification flow that expedites development and provides high verification reusability for follow-on derivative designs. This layered methodology raises the abstraction level for test creation to reduce the overall verification effort.

Services Structured to Serve You
Synopsys Professional Services offers flexible engagement models to match your requirements:

• Design assistance—We become members of your project design team to augment existing skills.
• Design outsourcing—We take on design tasks or projects that lie outside your focus or engineering capacity and execute in one of our design centers.
• Methodology assistance—We work collaboratively with you to instantiate new methodologies and flows.

Solving Your Toughest SoC Design Challenges
Synopsys Professional Services gives you access to highly qualified design resources that will help implement your complex SoCs. With expertise in every phase of chip design.built on experience with a wide range of tools, applications, process technologies, and methodologies.RTL design services from Synopsys Professional Services enables you to:

• Access highly experienced design teams to design and verify missing sub-systems or assemble complete SoCs with our extensive IP portfolio.
• Optimize your SoC architecture and micro-architecture for high performance.
• Increase your verification effectiveness with intelligent testbenches and coveragedriven simulations.
• Lower your risk of missing schedule or performance goals.
• Ensure high-quality designs with predictable project delivery and cost.
• Accelerate your learning curve with new tools and flows.
• Concentrate on your core competencies while taking advantage of ours.