Design Realization The Proven Approach to an Accelerated Tapeout

At-A-Glance

• Complement your design team with experts in SI, power, DFT, DFM, and verification
• Methodology and knowledge transfer
• Design handoffs at specification RTL or netlist stage with project support through tapeout
• Full concept to packaged parts capability

Value

• Very Deep Submicron (VDSM) Expertise: Greater than 75% of recent designs at 130nm, 90nm, or 65nm
• Experience: An average of more than 150 projects a year, and an extensive tapeout resume with 98% first pass silicon success
• Resources: Access to skilled designers, best-in-class tools and scalable compute infrastructure lets you optimize your resources

Whether due to unexpected changes in project staffing or a strategic outsourcing decision, augmenting your design capability with Synopsys’ design consultants can significantly improve your project productivity. In addition to design experience and tool expertise, Synopsys’ design consultants leverage proven design flows and methodologies, program management best practices, and an extensive compute infrastructure to meet your program objectives. In short, our consultants bring the knowledge and technology you’ve come to trust from Synopsys.

Specializing in the RTL to GDSII implementation of designs at 130 nanometers (nm) and below, Synopsys Professional Services addresses the deep submicron challenges of timing, power, signal integrity (SI), design-for-test (DFT), and design-for-manufacturability (DFM) to achieve predictable sign-off.

Our expertise with Synopsys Galaxy and Discovery platforms and the DesignWare IP portfolio will help you maximize chip performance (frequency, power, area, yield) and avoid costly iterations that prevent on-schedule tape-out. The significant experience of our consultants in designing some of the most advanced chips on the market enables us to be productive from the first day we’re on the job—to get your SoC completed on time and on spec.

Synopsys’ design services are flexible to best support your specific project and design objectives. Our consultants are supported by a worldwide network of design centers and design experts that can be leveraged to scale with a project’s changing needs. A program-driven combination of on-site and off-site execution offers an efficient balance between close interaction and knowledge sharing among all team members.

The joint design team can utilize Synopsys’collaborative design infrastructure. This secure, web-based environment enables the project team to leverage people and compute resources anywhere in the world, any time of the day. And access to an extensive server farm with scalable hardware and software resources really comes in handy during certain critical project phases.

Key Design Tools Used

• Design Compiler
• IC Compiler
• PrimeTime®/PrimeTime SI
• Star-RCXT™
• Hercules™

Typical Design Realization services include some or a combination of the following design tasks:

Block Optimization

• Micro-architecture and RTL code optimization
• Physical synthesis and block finishing
to GDSII

Full Chip Integration

• IP and block assembly and design capture for hierarchical designs
• Block and chip constraint promotion for hierarchical designs

Physical Design Optimization

• Interface logic modeling and static-timing analysis
• Signal Integrity analysis and prevention
• Power analysis, dynamic and leakage power optimization
• SI-aware, OCV-aware, and yield-aware place and route

Design Handoff

• Design activating can be fully collaborative, or you can handoff to Synopsys at virtually any level of abstraction (e.g., specification, RTL, netlist, or placed gates)

Expertise in Physical Design
As process geometries shrink, the physical design process becomes an increasingly important factor in determining chip quality, yield and reliability. That’s because the physical effects at advanced process nodes of 130nm and below become firstorder effects. When it comes to solving the complexities of physical design, there’s no substitute for experience. The most advanced tools in the hands of experienced engineers working with the best methodologies and infrastructure are the best ways to mitigate project risks.

Synopsys Professional Services has a long track record of successful chip tapeouts with and for our customers. Our design consultants leverage Synopsys’ leadingedge EDA technology and the Pilot Design Environment, a configurable and production-proven design flow with built-in utilities and methodologies for improving designer productivity. This design environment, configured for your specific design needs and proven on your chip, can be fully deployed during or after project completion to be leveraged on the next project.

• Early library and IP qualification and generation of missing views
• Flat, hierarchical, and “virtual flat” flows for various chip complexities
• Early floorplanning and power budgeting to address VDSM physical effects
• SI-aware, power-aware, and yield-aware place and route, placement optimization with physical synthesis, clock-tree synthesis, and extraction
• Chip finishing and analysis for VDSM effects, physical verification

Case Study: Advanced Methods Ensure First Pass Silicon Success
Chongqing Chongyou Information Technology Co. (CYIT), a leading Chinese fabless semi-conductor company, develops chips for China’s new 3G wireless communication standard, TD-SCDMA. Close cooperation and project management between Synopsys Professional Services and CYIT throughout the design process — from specification review through functional verification and chip implementation — ensured efficient project execution and tapeout success. The verification methods employed by Synopsys ensured high functional coverage for the multi-core chip and provided CYIT with an advanced, reusable methodology that improved the productivity of their verification environment. Producing a fully functional chip with the first prototypes represented an important milestone for CYIT and helped it achieve its next round of funding.

“As we planned this project, we wanted to work with the best technology and the best design services partner. We selected Synopsys’ Discovery Verification tools and Synopsys Professional Services and were rewarded with a successful chip tapeout and new methodologies that enhanced our design flow for our future designs.”

—Professor Zhen Jianhong,
General Manager, CYIT

Case Study: First Time COT, First Time Right
M-Systems is a leading developer of innovative, high volume data storage solutions for consumer applications such as mobile phones, PDA’s, set-top boxes, and embedded systems. Deploying a complete, pre-validated RTL-to-GDSII design flow from Synopsys enabled M-Systems to mitigate the risk of taking over the physical design of their chips. By providing additional design assistance through tapeout, Synopsys Professional Services facilitated a smooth chip implementation and first pass chip success. Synopsys’ design flow provided the best optimization in area and power consumption, two critical issues for high volume chips serving the consumer market.

“Building in-house physical design capability for a COT manufacturing model was accomplished in just 3 months with the help of Synopsys Professional Services. Functional prototypes from first silicon put us well on the way to meet our important customer deliveries.”

— Michael Mostovoy,
Director of ASIC Department, M-Systems

The complete success stories for Chongging Chongyou Information Technology and M-Systems are available at: www.synopsys.com/sps/success.html

For more information about Synopsys Professional Services, visit us on the web at www.synopsys.com/sps, contact your local sales representative or call 866.537.6654.