ARM Core Optimization and Integration Services

At-A-Glance

• Rapid implementations of all ARM soft cores optimized for customer-specified silicon processes
• SoC integration consulting and design services
• Advanced methodologies to provide a reusable integration environment for rapid derivative design implementation
• Configuration and deployment of the ARM-Synopsys Galaxy Reference Methodology

Value

• Predictability: Simple and deterministic route from RTL-to-GDSII
• Productivity: Industry-leading SoC/ARM design experiencein 130-nm, 90-nm, and 65-nm technologies
• Expertise: Global ARM Approved Design Center, co-developers of the ARMSynopsys Reference Methodologies
• Best practices for hardening highperformance, low-power ARM cores

Synthesizable or “soft” (RTL-based) IP cores provide advantages in the ability to configure and optimize the core to the requirements of the end-user or application. Through Synopsys Professional Services you will gain access to consultants who rank among the most knowledgeable in the industry for ARM core optimization, hardening, and integration. With dozens of ARM-based designs in 130nm or smaller geometries, our expertise will help you achieve the most efficient core optimization for your application. Customers receive fully modeled cores that have been “hardened” to the selected process technology and can be readily integrated by our consultants or customers into their SoCs.

Figure 1: ARM-Synopsys Galaxy Reference Methodology

Complementing our expertise in ARMbased designs, the ARM-Synopsys Galaxy Reference Methodology (RM) is the recommended flow for all ARM soft cores, including Intelligent Energy Manager™ (IEM) technology-enabled cores for low power applications. Co-developed by Synopsys Professional Services and ARM, the RM provides a tapeout-proven RTL-to- GDSII process for optimized ARM-based implementations. Our experience will provide optimized results in area, power, performance, and schedule for your specific technology and application.

Synopsys Professional Services is a global ARM Approved Design Center (ADC), tailoring each SoC implementation to customers’ specific requirements. Our consultants combine unique ARM technology-specific expertise with deep knowledge of Synopsys flows and advanced chip design to help developers optimize their SoCs.

Case Study: ARM Intelligent Energy Management (IEM) With Multi-VDD Product Development
When ARM needed to develop an ARM synthesizable processor with dynamic power efficiencies, it turned to Synopsys for core optimization and meeting schedule objectives. This design contained an ARM926ES with a multi-layer AMBAbus, Synopsys DesignWare cores, ARM IEM controller, AVS controller (from National Semiconductor), and multi-VDD and clock domains. Application-based (MPEG vs. MP3) monitoring and scaling supply voltage and CPU frequency pair were utilized to meet system performance requirements.

On-time project success required a highperformance design flow that enabled optimization of multiple-voltage supply domains within the core. Using Synopsys design methodologies in conjunction with Galaxy implementation tools and DesignWare IP, the project results were successful – a dramatic improvement in dynamic power consumption.

Figure 2. With IEM frequency and voltage scaling implemented, this chart represents
the percentage of power saved relative to a non-IEM mode of 1.2V VDD and 240MHz.
The operational power consumption percentage decreases dramatically as frequency
and voltage are are scaled downward.

ARM Core Hardening and Integration tasks include the following:

Core Configuration

• Optimize soft IP core for target application according customer specification
• Sub-systems can be created by adding buses and peripherals
• Functional simulation model is created in binary object-code format for security

Core Planning

• Initial mapping to gates in target technology
• Floorplanning – I/O placement, power planning, block placement
• Power and congestion analysis; testability and gross-timing analysis

Core Synthesis

• Logical or physical synthesis-based implementation and optimization
• Test synthesis and optimization
• Equivalency checking and simulation for compliance

Core Layout

• Detailed routing and clock-tee synthesis
• DRC/LVS
• Static timing analysis, signal integrity analysis, ATPG

Core Modeling

• Timing model creation
• Test model creation
• Physical model creation

SoC Integration

• Creation of an integration environment
• Assemble, analyze, and validate hardened cores
• Automated design capture, constraints promotion

Synopsys Professional Services: Helping to solve your toughest design challenges