Overview
Vera® is an industry-leading testbench automation product that increases design quality by finding simple as well as corner-case bugs, quickly. Vera allows engineers to create coverage-driven tests using advanced testbench concepts like constrained-random stimulus generation, real-time data and temporal checking and extensive analysis of functional coverage. Vera combines next-generation constraint solving and coverage analysis engines with a proven reference verification methodology and interfaces to leading Verilog and VHDL simulators. Vera supports the OpenVera® hardware verification language, including OpenVera Assertions, and is an integral part of the Synopsys Discovery™ Verification Platform.
- Key Benefits
- Very easy to learn, deploy and use across big or small projects
- Customer-proven reference methodology speeds deployment of reusable verification environments
- Next-generation constraints solver rapidly generates complex tests
- Powerful functional coverage analysis provides detailed feedback
- Real-time data and temporal checking enable reactive testbenches
- Supports all leading Verilog, VHDL and mixed-language simulators
- Accelerates verification ramp up with DesignWare® Verification IP
Design Challenge
Verification complexity tends to increase exponentially with design size. The continued advance of Moore's law has placed an enormous burden on today's verification engineer to continue to ensure that no bug is missed despite a significantly harder verification task, while at the same time managing with limited staff and compressed schedules.
Solution
The use of advanced verification methodologies and tools has been shown to increase first silicon success rates by finding more bugs, while at the same time improving verification productivity. Vera's constrained-random, coverage-driven methodology has become the gold-standard for functional verification, and is used by leading companies in multiple application domains. A recent survey1 of customers using Synopsys verification technologies showed that 89% of designs were functionally correct on first silicon - a much higher success rate than the industry as a whole. This success is further enhanced by increased verification productivity.
Finding Bugs Faster
Vera combines advanced language features, powerful verification engines, and a customer-proven methodology to enable the early identification of design bugs.
Constraint-Driven Test Generation
Vera's next-generation constraint solver is flexible and powerful, enabling users to implement a highly efficient constrained-random verification methodology. The solver uses formal techniques and multiple engines to provide unprecedented power to solve highly complex constraint sets. Users can quickly get solutions for thousands of simultaneous constraints, each with hundreds of random variables. The advanced solver enables users to thoroughly simulate a design's functionality, including corner-case scenarios, resulting in greater confidence in the design quality.
Figure 1 -Vera enables higher verification productivity with advanced language features
Functional Coverage Analysis
Functional coverage analysis provides a measure for the quality of a constrained-random verification methodology. Vera provides a powerful functional coverage engine that supports test grading, coverage accumulation across regressions and HTML-based coverage reporting. The functional coverage engine is integrated with the stimulus generation engine to support reactive test generation to eliminate redundancy in the regression suite.
Figure 2 - Vera finds more bugs with constrained-random, coverage-driven test
Reference Verification Methodology
Vera's powerful testbench engines are complemented by a proven reference verification methodology and layered testbench architecture that enables both new and experienced verification engineers to quickly create and deploy advanced, reusable, efficient verification environments. This methodology, developed and used by verification experts, helps users adopt industry best practices to get the best possible results from Vera. A detailed reference manual, pre-written testbench building blocks (base class library) and examples are provided with Vera.
Transaction-Level Interface to SystemC
Many designers create reference models in SystemC™ prior to coding RTL. Vera enables the use of a single, golden testbench to drive both SystemC and RTL representations of a design, ensuring consistency between the transaction-level model and the detailed implementation. Vera's transaction-level interface to SystemC enables users to quickly and easily connect a Vera testbench to a SystemC model and then re-use the same testbench when RTL is available.
VCS Verification Library
The VCS Verification Library provides the industry’s broadest portfolio of verification IP for today’s most popular bus and I/O standards. It also includes Design Views for DesignWare Star IP processor cores and thousands of memory models. Written in OpenVera, the VCS Verification Library supports the Synopsys Reference Verification Methodology (RVM). The verification IP in the library integrates easily into OpenVera testbenches to generate bus traffic, insert error conditions, and check for protocol violations. The Monitors provide extensive reports to show functional coverage of the bus protocols
- Related Verification Products
For more information about this product, please contact your local Synopsys representative or call 1-800-388-9125.
1February 2004 Vera Customer Survey by Synopsys, Inc.
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