Physical Scan Synthesis 1-Pass Physical Scan Ordering Technology Backgrounder

Contents

• Overview
• Introduction
• Challenges for DFT Implementation in the Physical Domain
• What is 1-Pass physical scan synthesis?
• Recommended physical scan flows
• Conclusion

Overview
As the design community moves to the complete adoption of physical synthesis solutions, it is becoming evident that testability must be taken into account at all stages of the design process. Successfully meeting all design requirements of multi-million gate designs requires the swift convergence of timing, area, power and test constraints. By bringing key physical functions into the front-end process, physical synthesis helps designers make fundamental decisions to architect the test structures early-on, while still being able to quickly satisfy timing, area and power constraints.

Introduction
In today’s complex designs, designing for test (DFT) is becoming an integral part of the design process to achieve testability goals of the design, enabling efficient manufacturing test. DFT Compiler supports a 1-Pass scan synthesis flow that tightly integrates scan with synthesis. It allows seamless scan insertion and meets all design constraints in the presence of test logic. While test synthesis is the most widely used DFT methodology in conventional ASIC design flows, it is becoming evident that testability must be addressed throughout the design process from RTL to the back-end placement and routing. One of the key technologies necessary to support this wide-ranging view of testability is that test synthesis be cognizant of floor-planning and layout issues and well integrated with physical design tools.

Traditional design flows that implement scan chain architecture in the physical domain pose bigger risks of the overall timing closure of the design. The DFT structures inserted in such flows create sub-optimal placement of functional design, and create routing congestion and increased area overhead. Typically, layout-based scanreordering solutions in the back-end place and route tools have been proposed to address many of the aboveproblems. However, these solutions rely on cumbersome flows to reorder scan chains after place and route outside of the design flow resulting in an increase of design iterations.

Recent innovations in synthesis technology have enabled the integration of DFT within the physical synthesis domain to support a significant new capability that takes into account routing congestion due to scan during physical synthesis and orders scan chains using physical placement information. This approach uses placement information and employs a timing optimized scan ordering algorithm to determine the scan chain order within the design flow. The tight integration of DFT within the physical domain ensures elimination of routing congestion and timing violations related to scan routing, and minimizes risk to timing, as well as DFT closure. This alsoincreases the routing predictability of the design.

Synopsys has recently introduced 1-Pass physical scan synthesis, which has all of DFT Compiler’s capabilities in the Physical Compiler environment along with 1-Pass scan ordering based on placement information.

Challenges for DFT Implementation in the Physical Domain
The following key issues will be addressed during the integration of DFT within the physical synthesis environment.

• Timing impact and placement of DFT logic added to fix test design rule violations.
• Ordering of scan cells in the design to reduce routing congestion and area overhead. Scan ordering should focus on reducing timing violations on the scan path, and in addition, consider blockages, obstructions and congestion within the design.
• Setup and hold time violations on scan path.
• Intelligent optimization to obtain timing convergence in the presence of new DFT logic and synchronization latches.
• Impact of scan connections on design routability under certain design characteristics.

What is 1-Pass Physical Scan Synthesis?
1-Pass physical scan synthesis in DFT Compiler and Physical Compiler provides a fully integrated flow that tightly links DFT with physical synthesis. It accounts for physical constraints such as placement, obstruction, etc. during DFT insertion, minimizes impact of DFT logic on timing, and provides faster timing convergence. Figure 1 illustrates the different steps in 1-Pass physical scan synthesis.

Test-Ready Physical Synthesis
Today’s 1-Pass scan synthesis in DFT Compiler takes into account setup time of the scan flip-flop and models additional load induced by the scan chain connection during synthesis to ensure early timing convergence.

At the time of physical synthesis, scan connections between registers are not present. If physical synthesis does not take into account the routing resources required to route scan connections, this reduces its ability to ensure routability of the design. On the other hand, if scan connections are considered during placement, this will result in sub-optimal placement of functional logic.

In order to satisfy, both of the above requirements, the physical synthesis process needs to be modified in such a way that it creates optimal placement, and at the same time, accounts for routing resources required for scan. Hence, DFT Compiler, along with Physical Compiler, supports the estimation of scan-congestion during physical scan synthesis. This capability increases the routability of designs that have a large percentage of registers.

DFT Logic Insertion Effects
In full-scan design methodology, additional logic is typically added to make asynchronous pins, as well as the clock pins of registers, controllable from primary inputs or to increase the observability of certain sections of the design. The capability exists today in DFT Compiler as AutoFix in the logical synthesis domain, where scan design rule violations for uncontrollable clocks and set/resets are automatically fixed by inserting DFT logic and simultaneously meet all timing constraints. However, this logic has to be incrementally placed and optimized for timing closure in the physical domain, resulting in a complex design flow and multiple iterations.

DFT Compiler along with Physical Compiler® provides a solution to insert additional logic to fix scan design rule violations as well as intelligently place the new DFT logic to reduce routing congestion while still meeting the design constraints. This solution ensures timing closure in the presence of DFT logic and also minimizes the number of design iterations.

Scan Chain Partitioning
The number of scan chains in a design is determined by various automatic tester equipment (ATE) and design constraints. Typically, to have multiple scan chains in a design, the scan cells are allocated to individual scan chains based on clock domains and user constraints. In DFT Compiler’s logical domain, scan-chains are partitioned and stitched typically based on clock domains by default, and within each chain, scan cells are connected in alphabetical order. Scan cells are allocated across chains within a same clock domain also in alphabetical order. Here, the problem is the lack of physical information associated with the scan cells allocation between multiple scan-chains. This approach will result in increased routing congestion after placement in the back-end tools and requires swapping scan cells across scan chains during re-ordering of scan chains.

In the Physical Compiler environment, scan-chain allocation within the same clock domain or across clock domains is based on physical information. During scan-chain partitioning, the tool takes into account the physical locations of the cells in the scan chain. The result is chains that take into account both the clock domains and the physical locations of the scan cells to produce a more optimal scan chain. This helps improve the timing and design rule checking in addition to reducing routing congestion for the design.

1-Pass Physical Scan Ordering
Once scan cells are allocated to a scan chain, they need to be ordered and stitched as a single chain. Since the order of scan cells in a chain does not matter for the purpose of scan testing, many existing techniques in the logical domain use simple logical names to reduce logical hierarchy crossing to connect scan cells within a scan chain. These scan connections, however, create routing congestion during the placement of the design. So scan chains are reordered in the back-end tools or using the ScanPlanner option within DFT Compiler, such that routing wire length is reduced.

DFT Compiler, along with Physical Compiler, uses the placement information to stitch and order the scan elements within scan chains the very first time and thus reduces design iterations to reorder the chains later. Besides the placement attribute, other DFT constraints such as clock domains, clock edges and user specifications are also addressed along with optimizing and reducing the amount of synchronization elements (lockup latches) added to the design during connection of scan elements across clock domains in a single chain. Figure 2 shows the advantage in using physical information to order scan chains, thus reducing the length of scan nets, which in turn minimizes routing congestion.

Optimization
Once the scan chains are connected, timing violations on the scan path need to be fixed before the DFT insertion process is complete. The physical scan synthesis process in DFT Compiler along with Physical Compiler optimizes the design for scan-path setup and hold timing violations.

These violations are fixed mostly by adding buffers and inverters on the scan path. After scan chains are stitched, local optimizations are performed to fix design constraints and quickly achieve timing convergence.

Recommended Physical Scan Flows
Synopsys recommends three different scan flows in the physical domain. They are namely:

• RTL-to-Placed-Gates Flow
• Gates-to-Placed-Gates Flow
• Scan Chain Re-ordering Flow

Figure 3: RTL2PG Flow

Gates-to-Placed Gates (G2PG) Flow
The gates-to-placed-gates flow can be used when an already available synthesized and "test-ready" netlist is available from Design Compiler™/DFT Compiler, and Physical Compiler is used to further place the design, and perform 1-Pass physical scan ordering.

Here, the design is first synthesized with scan from the RTL in Design Compiler using wire-load models, and then the synthesized netlist is further placed and optimized in Physical Compiler. Scan-chain ordering is performed within the Physical Compiler environment to stitch the scan chains based on physical information, thus optimizing the design for routability as well as achieving timing closure. Figure 4 shows the gates-to-placed-gates flow with sample scripts and commands.

Figure 4: G2PG Flow

Scan Chain Re-ordering Flow
The capability of DFT Compiler within Physical Compiler is more optimized and tailored for better quality of results for 1-Pass scan ordering, i.e., to build scan chains from initial specification based on physical information.

However, Synopsys' physical scan synthesis solution also supports re-ordering of scan chains based on placement information if the chains are already routed in the logical domain by DFT Compiler or by any other third-party scan-stitching tools. The advantages of physical scan partitioning in allocating scan cells to different scan chains cannot be utilized in this flow.

The input to DFT Compiler/Physical Compiler is a netlist with scan chains already routed. However, this flow needs the user to identify the already existing scan ports and non-scan flip-flops if any, as well as tell DFT Compiler that scan already exists. Figure 5 shows the scan re-ordering flow with sample scripts.

Figure 5: Scan Chain Re-ordering Flow

Conclusion
As the design community moves to the complete adoption of physical synthesis solutions and flows, EDA tools must include DFT as an integral part of the entire RTL to manufacturing test flow. Synopsys physical synthesis solution addresses the challenges imposed by DFT insertion and scan ordering from RTL to the physical domain.

This Synopsys physical synthesis solution delivers 12%-18% reduction in congestion as seen in many customer designs. Figure 6 shows the difference in length of scan-nets as well as the benefits of the scan partitioning using physical information on a customer design.

The key advantage of the Synopsys DFT Compiler/Physical Compiler solution is its tight integration with physical synthesis to minimize the impact of scan-placement and ordering on the overall design timing. In this solution, better congestion estimation due to scan nets increases routing predictability. Scan-chain partitioning and ordering reduce congestion and minimize timing violations. Lastly, the intelligent placement of DFT logic and optimization reduces the impact of DFT on timing closure.

Integrating the above capabilities within DFT and deploying them throughout physical synthesis allows designers to get an accurate and early view of testability, timing, area and power constraints.

Default Scan Ordering

Placement-based Scan Partitioning and Scan Ordering

Figure 6: Placement Based Scan Ordering and Partitioning