Sign-Off Archives

Press Releases

• STARC Adopts Synopsys PrimeTime VX as the Variation-Aware Timing Tool for Its STARCAD-CEL Methodology
• Synopsys, Altera and TSMC Collaboration Delivers Industry-Leading 45-Nanometer Extraction Accuracy
• Toshiba Standardizes on CCS Technology at 65nm to Improve Accuracy and Designer Productivity
• Synopsys Star-RCXT Extraction Solution Achieves Industry's Broadest 65-Nanometer Qualification and Usage
• Synopsys Boosts Designer Productivity by Launching Liberty NCX Characterization Solution
• Synopsys Enhances Library Compiler to Put Current-Source Models Within Reach of Every Designer
• Virage Logic Adds Liberty Composite Current Source Model Support to Memory and Logic IP
• Synopsys Enables STMicroelectronics to Achieve First-Silicon Success for 65-nm Dual High-Definition MPEG-4 Decoder
• Synopsys PrimeTime and Star-RCXT Solutions Deployed at Fujitsu as Standard for 65-nanometer Sign-off
• TSMC and Synopsys Announce CCS Model Support for TSMC'S 65-Nanometer Process
• Synopsys Donation of Variation-Aware Extension to SPEF Format Approved by IEEE 1481 Working Group
• Cypress Deploys Synopsys PrimeRail to Speed Tapeout of Mobile Phone IC Design
• Synopsys Extends Liberty Modeling Standard to Enable Variation-Aware Design
• Synopsys Extends PrimeTime and Star-RCXT with Statistical Capabilities to Address Variation-Aware Design Challenges
• TSMC Reference Flow 7.0 Incorporates Synopsys’ IC Compiler
• Industry Leaders Join Synopsys and Si2 to Advance Liberty Modeling Standard
• Synopsys Unveils NanoTime Next-Generation Transistor-Level Static Timing Analysis Solution
• Altera Deploys Star-RCXT Extraction Tool and HSIM Simulator to Achieve Silicon-Accurate 65nm Designs
• Synopsys and Si2 Drive Open-Source Modeling to Next Level by Forming Technical Advisory Board

Articles

• EE Times Asia: Flexible Analysis is Key to Power Integrity
• EE Times Asia: Achieve Low-Power Design Success at 65nm
• EE Times: Power integrity analysis for billion-transistor full-custom designs
• EE Times: Synopsys donates technology to Accellera low-power effort
• EE Times: Accellera Rolls Power Plan
• Test & Measurement: Limits of Test Time Reduction
• EE Times: How Much Test Compression is Enough?
• EE Times: Critical Area Optimizations Improve IC Yields