Key Benefits

• Minimize tape-out risk by providing complete verification coverage.
• Easy to use solutions shorten time-to-results of multi-million gate designs
• Verifies entire SOC, including logic, datapath, custom macro, memory and I/Os

Design Challenges
Synopsys tools address the need for equivalence checking of your large complex SoCs, including memories, full custom logic and I/Os. With unique and patented technologies such as Hier-IQ, datapath targeted solvers, and symbolic simulation, users obtain the most comprehensive equivalence coverage available.

Solution
Equivalence checking tools enable you to quickly prove functional equivalence of your ultra-large ASIC, SoC and FPGA designs as those designs are implemented. Complex designs use numerous optimizations and are composed of extensive datapath, memory and full-custom blocks. The Synopsys' functional verification suite includes Formality for complete synthesis-flow verification and ESP for full-custom, memory verification. Formality and ESP offer leading performance, are easy-to-use, and combine to provide full-chip, RTL-to-transistor functional verification coverage.

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