HELPING YOU DESIGN THE CHIP INSIDE Products and Solutions ---------- SOLUTIONS ---------- Eclypse Low Power Solution Galaxy Design Platform • Design for Low Power • Design for Test • Design for Yield • RTL Synthesis • Physical Implementation • Sign-Off • Liberty CCS • SDC • Milkyway Discovery Verification Platform • Analysis and Debug Tools • Low-Power Verification • System Analysis & Design • Smart RTL Verification • Functional Equivalence Checking • Mixed-Signal • Languages Intellectual Property (IP) • DesignWare Library • DesignWare Verification IP • DesignWare Cores • DesignWare Star IP • DesignWare Foundry Libraries • IP Reuse Tools Design for Manufacturing • Design-Yield Analysis • Mask Synthesis • Mask Data Preparation • Lithography Verification • TCAD • Manufacturing Yield Management Professional Services • Tool and Methodology Deployment • Pilot Design Environment • Flow Optimization • Implementation • Verification Consulting • Concept to Parts • Core Hardening ---------- PRODUCTS ---------- BSD Compiler: Test synthesis Cadabra: Cell creation Calibration Library CATS: Mask data preparation Circuit Explorer: Analysis & Optimization coreAssembler coreBuilder coreConsultant CosmosLE: Layout design environment CosmosScope: Waveform analysis CosmosSE: Schem. design environment DC Ultra: RTL synthesis Design Analyzer: RTL synthesis Design Compiler: RTL synthesis DesignWare: Design & verif. IP DesignWare Virtual Platforms DFT Compiler MAX DFT Compiler: Test synthesis DSSA Sentry Enterprise: Layout editor ESP: Transistor-level Equivalence Checking Formality: Funct. equiv. checking Hercules: Physical verification HSIM HSPICE: Accurate circuit simulation IC Compiler IC Workbench Innovator: SoC / system modeling JupiterXT: Design planning Leda: RTL checker Library Compiler: Library compilation Liberty NCX: CCS Characterization Magellan: RTL formal verification Memory Solution Milkyway: Design database MVRC MVSIM NanoChar: 90 nanometer & below characterization NanoSim: Fast circuit simulation NanoTime Odyssey Defect/Odyssey YMS Paramos Pilot Design Environment Pioneer-NTB: SystemVerilog testbench automation Power Compiler: Power optimization PrimePower: Power analysis PrimeRail PrimeTime PX PrimeTime: Static timing analysis PrimeTime SI: Signal integrity analysis PrimeYield Tool Suite Proteus OPC PSM-Create & PSM-Check Raphael Raphael NXT Recipe Manager and Editor (RME) Saber: Multi-tech. simulation Scirocco: VHDL simulation Seismos Sentaurus Device Sentaurus Lithography Sentaurus Process Sentaurus Structure Editor Sentaurus TFM Sentaurus Topography Sentaurus Workbench SiVL-LRC: Lithography verification SpiceCheck SpiceExplorer Star-RCXT: Full-chip RC extraction Star-RCXT VX Star-SimXT: Fast circuit simulation System Studio: DSP algorithm design Taurus-Medici Taurus-TSuprem4 TetraMAX: ATPG VCS: Comprehensive RTL Verification VCS MX: Mixed-HDL simulation Vera: Testbench automation WaveView Analyzer DESIGN IMPLEMENTATION VERIFICATION INTELLECTUAL PROPERTY DFM/TCAD DESIGN SERVICES  SABER HOME Saber Overview  FEATURED INDUSTRIES Automotive Aerospace  METHODOLOGIES Robust Design Harness Design & Simulation Mechatronic Design & Simulation  CAPABILITIES VHDL-AMS Modeling Simulation & Analysis Design  RESOURCES Press Releases Technical Resources Partners & Interfaces Contact us Saber Technical Resources Paper & Presentations SAE Publication › 2008-01-1031 Model-Based FlexRay Designs (C&S) › 2008-01-0901 Robust Design of VVT (GM) › 2008-01-0898 Power Network Design (Jaguar) › 2008-01-0288 Virtual Mfg/DFSS with Distributed Computing (GM) › 2007-01-1636 FlexRay Physical Layer & Signal Integrity Analysis (University of Applied Sciences) › 2007-01-1640 Valvetrain Cam Phaser (Createch) › 2007-01-1592 Modeling/Simulating Hybrid Electric Vehicles (Synopsys) › More © 2005-2008 SAE International. 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Datasheets › Saber Overview – Automotive › Saber Sketch › Saber Overview – Aerospace › Saber Simulator › Vehicle Powernet Design › Saber Scope Datasheet › Hybrid Vehicle Design and Verification › Saber Harness › In-Vehicle Network Design › Saber MAST Newsletter "The Cutting Edge" › The Cutting Edge Volume 6 (Jan 2008) › The Cutting Edge Volume 3 › The Cutting Edge Volume 5 › The Cutting Edge Volume 2 › The Cutting Edge Volume 4 Recorded Presentations Web seminar › Using Simulation to Implement a Robust Design Flow Articles › EE Times: Synopsys, Zuken tie simulation to boards › Automotive Design Line: Simulation-based design integration improves hybrid vehicle reliability › DesignFAX: System Simulation › SAE Off Highway Engineering: Design challenges of off-highway hybrids › Automotive Design Line: Verification methodology provides robust embedded automotive electronics design › More Training › Saber Designer Mixed-Signal & Mixed-Technology Simulation › MAST Modeling › Robust Design Workshop › Power Electronics Robust Design Workshop › Advanced Saber/MAST CONTACT US  | FEEDBACK  | LOCATIONS  |  PRIVACY POLICY  |  LEGAL

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