IC Compiler Archives

Press Releases

• Synopsys IC Compiler Routing Qualifies for TSMC's 45-Nanometer Process
• Synopsys Introduces Industry's First Concurrent Hierarchical Design System With Latest IC Compiler Release
• Synopsys IC Compiler Successfully Employed by Matsushita for First 45-nm SoC Design Tapeout
• Toshiba Standardizes on Synopsys IC Compiler with Release of Orion V1.0 Design Kit
• Synopsys IC Compiler Used By NEC Electronics for Tapeout of Gigahertz Processor
• IC Compiler 2007 Release Continues Technology Innovation
• Synopsys Enables STMicroelectronics to Achieve First-Silicon Success for 65-nm Dual High-Definition MPEG-4 Decoder
• Renesas Technology Chooses Synopsys IC Compiler Solution for SoC Design Flow
• Silicon Optix Selects Synopsys IC Compiler for 90nm Design
• Progate Tapes Out Advanced Mobile Communications Chip Using Synopsys IC Compiler
• Synopsys Introduces 'MinChip' Technology Delivering Smallest Possible Chip Size For Volume Applications
• Synopsys IC Compiler Enables Toshiba's Tapeout of High-Performance 90-nm Consumer Wireless Chip
• Exar Selects JupiterXT Power Network Synthesis to Achieve Optimized Power Layout
• Synopsys PrimeYield LCC Links to IC Compiler for Automated Correction of Lithography Problems
• Synopsys Delivers First 65-nm Reference Flow for IBM, Samsung and Chartered
• TSMC Reference Flow 7.0 Incorporates Synopsys IC Compiler
• IC Compiler Completes Tapeout of High-Density Sunplus Consumer Design
• Micronas Tapes Out HDTV Chip with Synopsys IC Compiler
• Synopsys Continues IC Compiler Momentum with 2006.06 Release
• JupiterXT Tool Cuts Prototyping and Implementation time on Cavium Netwworks’ OCTEON MIPS64 Processors
• Hisilicon Technologies Adopts Synopsys Galaxy Design Platform for Low-Power Design
• STARC Adopts IC Compiler to Boost Efficiency of Production Flow

Articles

• SCDsource: Synopsys rolls next generation IC router
• Semiconductor Int'l: Synopsys Unveils Faster Router
• EDA DesignLine: Design Challenges Drive Need for New Routing Architecture
• EE Times: Early relief for 45-nm routing congestion
• EE Times Asia: Achieve Low-Power Design Success at 65nm
• EE Times: Power integrity analysis for billion-transistor full-custom designs
• EE Times: Synopsys donates technology to Accellera low-power effort
• EE Times: Accellera Rolls Power Plan
• EE Times: How Much Test Compression is Enough?
• EE Times: Critical Area Optimizations Improve IC Yields