Overview
ESP products serve a critical full custom design verification market, which is growing as more memories and custom logic are incorporated into SoCs. ESP's unique transistor-level formal verification technology has been successfully deployed in a number of top-tier companies. ESP solutions combined with Formality offer customers equivalence checking solutions from a single supplier which will enable them to achieve faster and more comprehensive functional verification of custom circuits, embedded memories, complex I/Os and system-on-chip (SoC) designs.

Key Benefits

• Behavioral model support
• Direct transistor-level support
• Considers timing dependent functionality

Design Challenges
Major challenges for full custom design verifications are coverage, parasitics effect on circuit functionality, and functional consistency between the RTL model used for system-level simulation and the transistor-level netlist that is implemented.

Solution
Based on three major technologies - symbolic simulation, CKT, and hierarchical compression – the ESP products provide the most complete functional equivalence checking solution for complex full custom designs. ESP is targeted at verifying designs such as memories, custom macros, library cells, and I/Os.

Symbolic simulation increases the coverage of verification and can be applied to all levels of design abstraction - from SPICE, switch, gate, RTL and behavior. Unlike other solutions, ESP allows designers to directly verify their non-synthesizable simulation models, eliminating the need to recreate a model, which can be error prone. CKT allows equivalence checking of transistor level netlist without the use of gate model extraction. Rather than using a template-based approach, where transistor network is matched to a pre-defined gate-level model, ESP directly verifies the SPICE netlist against the simulation model. ESP considers transistor parasitics such as it’s width, length, and the process technology, which results in a much more accurate verification that is easy to use. Hierarchical compression enables equivalence checking of very large memories including 1G DRAM.

ESP can verify all types of digital circuits including asynchronous logic, latch-based designs, self-timed logic, dynamic circuits, pre-charge and domino logic with considerations for its timing dependent functionality. ESP verifies structurally different implementations including retiming, pipeline depth, and redundancy.

Related Products

• Formality

For pricing information, please contact your local sales office.
For more info about ESP, contact functional_verification@synopsys.com

Back to Discovery Verification Platform