VCS Verification Library

The VCS Verification Library builds on the proven DesignWare Verification IP by adding support for the Verification Methodology Manual (VMM) for SystemVerilog using the Reference Verification Methodology (RVM). Support for Native Testbench in VCS provides up to 5X improvement in runtime performance.

The VCS Verification Library is the industry's broadest portfolio of standards based verification IP which integrates easily into Verilog, SystemVerilog, VHDL and OpenVera testbenches to generate bus traffic and check for protocol violations. Monitors provide coverage reports to show functional coverage of the bus protocols.

Verification IP and Verification Methodology Manual (VMM) for SystemVerilog
The Verification Methodology Manual for SystemVerilog, co-authored by Synopsys and ARM, defines a coverage-driven, constrained random methodology that speeds time to reach coverage goals. DesignWare Verification IP provides extensive support for the VMM and includes scenario generators and transactors to significantly reduce testbench development time.

VCS Verification Library and Native Testbench
VCS Verification Library supports VCS. Native Testbench (NTB) technology. VCS compiles the Verification IP natively to provide up to five times faster runtime performance. VCS Verification Library also supports Pioneer NTB, Synopsys testbench automation tool, to give high performance in Mentor Graphics ModelSim and Cadence NC-Sim environments.

The verification IP in the VCS Verification Library is also included in the DesignWare Library or is available as stand-alone suites.

  VCS Verification Library Datasheet

• Broadest verification IP portfolio in the industry
• Delivers 5X simulation performance improvement with VCS
• Supports proven verification methodology for SystemVerilog
• Includes example testbenches to accelerate learning and speed testbench development