Welcome to the DesignWare Technical Bulletin This quarterly newsletter brings you up-to-date on recent DesignWare IP news, from product announcements to upcoming seminars.
Connecting a Standard SRAM Device to an AMBA 3 AXI Subsystem Using the DesignWare Generic Slave
When adding an SRAM to an AMBA 3 AXI-based system, figuring out how to interface the SRAM to the bus can be a challenge.
Many of the available off-the-shelf memory controllers are not specifically designed to control SRAM devices and include logic for controlling SDRAM,
Flash, and other devices that require more control logic than that required by an SRAM device.
This application note describes the DesignWare Generic Slave and outlines how to use it to connect a standard DRAM device to an AMBA 3 AXI subsystem.
DesignWare Verification IP Quickstart for AMBA 3 AXI: A New View into Documentation
One of the biggest challenges when acquiring verification IP for a verification environment is integrating and using the verification IP.
This can be even more challenging when adopting a new verification IP along with a new verification methodology.
Based on the feedback received from many DesignWare IP customers,
this Quickstart consists of guidelines and new examples to help ease the adoption of the DesignWare Verification IP for AMBA 3 AXI in a SystemVerilog environment.
FEATURED WHITEPAPERS
Accelerating Software Driver Development Using Virtual Platforms: A USB Case Study
Software development is becoming the dominant cost factor in electronics design.
The ability to parallelize the traditional sequential process of software development trailing hardware development is crucial to get products to market as early as possible.
Virtual platforms are introduced as an effective development instrument for software driver, middleware and OS development.
Using an example of the Synopsys DesignWare® Hi-Speed USB On-The-Go controller,
this paper demonstrates how the specific challenges in software driver development of complex IP blocks - early availability, visibility and control - can be addressed with virtual platforms.
TRAINING AND EVENTS
Free DDR IP technical webinar series:
Buying Time: Using Signal Integrity and Common Sense to Meet Timing Margins for High Speed Memory Interfaces
October 15, 2008
Register Now
Now available on-demand
Decoding the Real Low Power Benefits of DDR for Embedded Applications
View Now
Avoiding the Landmines When Using a DDR Interface on Your Next SoC
View Now
