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ISSUE #: Q3-08
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What

WHAT'S NEW IN DESIGNWARE IP

New release of DesignWare Verification IP for OCP

The 1.40a release of DesignWare OCP Verification IP (VIP) includes a number of new features. It is available for download from http://www.synopsys.com/products/designware/vip_solutions.html

Support for non-default tie-offs
This feature applies for VMM and HDL testbenches.
Non-default tie-off values may now be specified for signals that are not specifically configured in the interface. The tie-off value for a signal tells a component that it should behave as if the signal is present and what the value of that signal should be set to.
Impact to Existing Testbenches: None.

Support for Write Response Extension (2.2wrext)
This feature applies for VMM and HDL testbenches.
The Master and Slave transactors now support an extension (2.2wrext) of the standard OCP Write Response model noted in the "Protocol Options" section of the Open Core Protocol Specification, Release 2.2; Document Revision-1.1. This extension provides the capability for an OCP interface to issue responses to all requests except posted writes. To enable this feature, set the new m_en_max_rand_ocp_ver configuration property to "UNLIMITED".
Impact to Existing Testbenches: None.

Restricting randomized configurations specific versions of OCP
This feature applies for VMM testbenches.
One of the features of the DesignWare Verification IP is that you can randomize the configuration. If you do this, the new m_en_max_rand_ocp_ver property will constrain the configuration values to comply with a specific version of OCP (2.0, 2.1, or 2.2).
Impact to Existing Testbenches: None.

New transaction properties and transaction phase status enum
This feature applies for VMM and HDL testbenches.
Dataflow transaction objects now include start_time and end_time values. The VIP automatically fills in the start time and end time for each OCP transaction (values are in simulation time units).
Impact to Existing Testbenches: None.

New HDL (command-based) examples demonstrate OCP 2.0, 2.1, and 2.2 features
These Verilog and VHDL examples use the VIP models connected together to demonstrate OCP setup and basic operation. The examples are as follows:

  • ocp20_sys_vlog/vhdl (demonstrates block burst transactions)
  • ocp21_sys_vlog/vhdl (demonstrates thread-based burst transactions)
  • ocp22_sys_vlog/vhdl (demonstrates tag-based burst transactions)