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Overview
The Synopsys DesignWare® USB 1.1 Host Controller (OHCI) Synthesizable IP is USB IP Host core that ASIC/FPGA designers can use to implement a complete USB OHCI Host Controller.
The Host runs at Full and Low Speeds and is compatible with USB 2.0 and the Open HCI 1.0 specifications.
By utilizing Synopsys' production-proven USB IP, designers can significantly reduce development time and engineering risk, and bring their USB-based solutions to market faster.
The Host can be customized and optimized for a specific application. In addition, the design can be easily migrated to almost any technology in a relatively short period of time.
Synopsys' USB IP can be easily bridged to any industry-standard bus such as PCI.
Designers can choose between a Virtual Component Interface (VCI) or a HCI interface, which shields the designer from the complexities of the USB host controller,
and makes it easy to integrate the USB IP into the customer's target application
Highlights
- Silicon proven
- USB 1.1 Compliant
- VCI, AHB or Native interface
- Compatible with Open HCI 1.0 specification
- Available in Verilog
- Supports low-speed and full-speed devices
- Configurable root hub supporting up to 15 downstream ports
- Configuration data stored in Port Configurable Block
- Single 48-MHz input clock
- Simple application interface facilitates bridging the host to other system bus such as PCI, and the integration of the controller with chipsets and microcontrollers
- Integrated DPLL
- Support for SMI interrupts
- Approximately 25K gates with 2 ports
- Test Environment includes USB compliance tests and Bus Functional Models
For questions or comments on DesignWare, Contact Us
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