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Overview
The DesignWare® PCI Express® to AMBA™ 2.0 AHB™ Bridge Core (PCIe®-AHB Bridge) enables designers who use the AMBA 2.0 AHB on-chip bus to easily add PCI Express external connectivity to their AMBA 2.0 AHB-based System-on-Chip (SoC) devices.
The PCIe-AHB Bridge is designed to work in conjunction with the portfolio of silicon proven DesignWare Cores for PCI Express 1.1 including Endpoint, Root Complex, and Dual Mode.
The PCIe-AHB Bridge is configurable and scalable to meet multiple application requirements of today's complex SoC designs.
The PCIe-AHB Bridge handles all the issues needed to successfully connect these two protocols together.
The PCIe-AHB Bridge provides the standard AMBA AHB interfaces and the bridging logic that maps the connection between the SoCs AMBA AHB interconnect and the native interface of the DesignWare PCI Express portfolio of cores.
The PCIe-AHB Bridge optionally supports up to three AHB interfaces, one for an AHB master, one for an AHB slave, and one for Data Bus Interface (DBI) access to the PCI Express core.
The AHB Master and Slave interfaces of the PCIe-AHB Bridge enable the PCI Express interface to be an AHB slave or an AHB master.
The master and slave interfaces handle AHB protocol, internal slave and master control for generic request and responses, a packet composer, and a packet decomposer.
The SoC can read from, or write to registers within the DesignWare PCI Express core through a slave DBI interface.
The AHB channel read/write address directly control the address mapped inside the PCI Express cores' CDM register map.
The PCIe-AHB Bridge master interface handles all types of inbound transactions received by the PCI Express interface to the SoC.
This enables a remote PCI Express device connected on the link to send a transaction through the PCIe-AHB Bridge from a PCI Express device to any AHB slave within the SoC.
The PCIe-AHB Bridge slave interface handles all types of outbound transactions from the SoC AHB interconnect that are targeted to a remote PCI Express device connected to the PCI Express bus.
Applications
The Bridge supports the function, area and throughput requirements of a wide variety of applications including:
- Data Communications
- Telecommunications
- Storage Area Networks
- LAN Interfaces
- Graphics Devices
- Wireless Devices
- Other I/O applications
DesignWare PCI Express to AMBA 2.0 AHB Bridge
Highlights
- AHB master and slave interfaces for inbound and outbound PCI Express requests
- Supports full PCI Express configuration, I/O requests, traffic class (EP, TD, etc.) through Bridge
- AHB slave interface for PCI Express core CDM register access through the PCI Express core's DBI interface
- Programmable buffer sizes for AHB Master and Slave requests and response queuing
- Independent programmable clock rates for the PCI Express core and AHB subsystem
- Programmable maximum number of inbound and outbound read requests for AHB
- All burst-sizes supported for both AHB Master and Slave interfaces
- Programmable burst lengths to support 4K read/write burst over AHB Master and Slave interfaces
- Independent maximum read request and transfer sizes between AHB and PCI Express (transfers can be split into multiple transfers)
- Response AHB Slave request gathering from split PCI Express completions
- Response AHB Master request gathering from multiple AHB responses
- Out-of-order transactions for transactions with unique Master IDs
- Interrupt and Message handling
- Response error mapping between PCI Express errors (UR, CA, CRS, poisoned, and ECRC error) and AHB Slave response errors
- Response error mapping between PCI Express errors (UR, CA, CRS, poisoned, and ECRC error) and AHB Master response error
- Bridge handles completion time outs
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