DesignWare DDR3/DDR2/DDR Memory Interface IP Solutions Press Release: Synopsys Launches Silicon-Proven DDR3 and DDR2 IP Solutions for SoC Designs

Overview
The DesignWare® DDRn Memory Interface is a family of complete system-level IP solutions for SoCs requiring an interface to the broad range of high performance DDR3, DDR2 and DDR SDRAM memory subsystems. Optimized for improved data bandwidth, low power and enhanced signaling features, the complete DesignWare DDRn IP solutions include a choice of scalable digital memory controller, an integrated hard macro PHY delivering memory system performance of up to 1600 Mbps per bit, and verification IP.

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See how we verify the DesignWare IP for DDR2/3 PHY and Controllers See firsthand the test equipment and custom boards developed and used by Synopsys to verify our DDR IP. Witness full speed write and read data eyes, at speed functionality testing, duty cycle and phase error tests and jitter analysis results.

With the limitless appetite for bandwidth in a growing number of markets, from networking equipment to Digital/HD TVs, DDRn SDRAMs are being deployed across a broad spectrum of applications. Designers need the flexibility to configure a memory solution that is adaptable for their specific applications and design flow constraints. The DesignWare DDRn Memory Interface IP solution fulfills this need, with an interface that can be implemented with commonly used design tools. In addition to deployment flexibility, the controller and PHY IP components are endowed with multiple features that help reduce development time and increase performance. Finally, each generation of DesignWare Memory Interface IP supports two generations of DDRn SDRAM (e.g., DDR3/DDR2 and DDR2/DDR) to reduce risk and provide flexibility for the volatile DRAM market.

• DDR2/DDR
  DDR2/DDR architecture operating at up to 1066Mbps. This is the preferred IP for use with 512Mb or smaller DRAMs.

• DDR2/3-"Lite"
  An area & feature optimized DDR interface IP solution operating at up to 1066Mbps using DDR2 or DDR3 SDRAMs. It is ideal for SoCs that are currently interfacing to DDR2 but want to have the option of migrating to DDR3 when it comes more cost effective. PVT compensated I/Os are fully compatible with DDR3 SDRAMs.

• DDR3/2
  High-performance PHY & controller architecture operating up to 1600Mbps. This product line offers a wealth of in-system calibration capability to ease timing budget constraints with the ever shrinking data eyes. In addition, the DDR3/2 products support 4:1 and 2:1 modes (width of internal buses : memory channel bus) easing timing closure requirements at the higher DDR3 clock frequencies.

For each DesignWare DDRn interface IP solution, Synopsys provides two controller cores that are designed to function seamlessly with the DDRn PHY:

• DDRn Memory Controller (MCTL)
  The MCTL is a full-featured, general-purpose memory controller which converts host port memory requests into DDRn transactions managing all DDRn protocol requirements such as bank precharge/activate, ODT, and refresh. The MCTL includes support for up to 32 host ports, flexible port arbitration, and advanced command reordering/scheduling to optimize DDRn data bus utilization. The MCTL's flexibility and high performance make it the best controller choice for most memory subsystems.

• DDRn Protocol Controller (PCTL)
  The PCTL is a low-latency, high performance single port controller which converts host port memory requests into DDRn transactions managing all DDRn protocol requirements. PCTL optimizes DDRn precharge/activate commands across all banks to maximize DDRn data bus utilization. The PCTL's lean design and high performance make it ideal for memory subsystems with unique scheduling or application bus requirements requiring a custom designed memory scheduler.

Highlights

• SDRAM Controller Features
  • Implementation choices: lean and efficient DDRn protocol controller core or full-featured multi-port memory controller core with optimized scheduling operation
  • Configurable address and data widths, buffer depths, ECC, memory addressing, pipelines and PHY control
  • Integrated calibration and data training for DesignWare DDRn PHYs
  • Support for native interfaces or AMBA® 3 on-chip bus interfaces
• PHY features
  • Fully integrated, hard macro PHY that includes application specific SSTL I/O library
  • DDR3 speed grades up to 1600 Mbps
  • DDR2 speed grades up to 1066 Mbps
  • Modular architecture for flexible placement and flexible I/O ring design
• DesignWare Verification IP
  • Verifies all configurations of the DDRn Interface including the PHY and memory controller
  • Supports directed and constrained random traffic generation
  • Provides functional coverage of transactions and coverage of the compliance checklist

Applications

• Set Top Boxes
• Digital / HD TV
• DVD / PVR recorders/players
• Networking Routers & Switches
• Printers/Scanners
• Portable video players
• Game Consoles
• Camcorders
• Wireless routers
• Digital media players
• Car navigation systems