Faculty in the School of ECE at Purdue University use a variety of Synopsys tools to facilitate a wide range of VLSI and Nanotechnology area research leading to 40 publications in over 20 journals and conference proceedings during 2007 and the first half of 2008. Tools most often cited include Medici, Taurus, Design Compiler, HSPICE, and Nanosim. In this article we highlight three faculty whose collective work led to a majority of these publications.

Prof. James Cooper reports that analysis in Medici made it possible to design Silicon Carbide power DMOSFET transistors, subsequently fabricated and tested at the Birck Nanotechnology Center, which achieved the lowest specific on-resistance ever demonstrated in a 1 kV class MOSFET [1-4]. Prof. Muhammad Alam has used Medici extensively in the modeling of devices for Silicon Nanowire Biosensors [5], analysis of degradation of drain-extended NMOS transistors [6], and in analyzing the characteristics and scaling of capacitorless single transistor “Z-RAM” memory cells [7-8]. The research group of Prof. Kaushik Roy has reported advances in several areas that were supported by Synopsys tools. Device simulations in Medici were used in obtaining an improved Static Noise Margin model for SRAM designs [9]. Medici and Aurora were used to accurately model body bias effects in a sub-100nm SRAM design which uses body bias to reduce parametric failures [10]. Taurus was used to derive IDS-VDS characteristics for dual independent gate FinFETs for which a cell library was created. The cell library was characterized, and Library Compiler and Design Compiler were used to implement a low power synthesis flow based on the FinFET technology. Various aspects of the FinFET work are documented in several papers [11-16]. Work in advanced arithmetic and DSP architectures benefitted from a range of tools including Design Compiler, HSPICE, and Nanosim [17-23].

For more information on this work, please refer to the paper presented at the 66th Device Research Conference: http://drc.ee.psu.edu/abstracts/vnikam-20080319-235.pdf

[1] A 1-kV 4H-SiC Power DMOSFET Optimized for Low on-Resistance. A Saha, JA Cooper - Electron Devices, IEEE Transactions on http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?tp=&arnumber=4317746&isnumber=4317723

[2] Demonstration and Characterization of Bipolar Monolithic Integrated Circuits in 4H-SiC. J-Y. Lee, S. Singh, and J. A. Cooper, to appear in IEEE Transactions on Electron Devices, 2008.

[3] Numerical Study of the Turn-Off Behavior of High-Voltage 4H-SiCIGBTs. T. Tamaki, G. G. Walden, Y. Sui, and J. A. Cooper, to appear in IEEE Transactions on Electron Devices, 2008.

[4] Optimization of On-State and Switching Performance for 15 – 20 kV 4H-SiC IGBTs. T. Tamaki, G. G. Walden, Y. Sui, and J. A. Cooper, to appear in IEEE Transactions on Electron Devices, 2008.

[5] Design Considerations of Silicon Nanowire Biosensors. PR Nair, MA Alam - IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007
http://cobweb.ecn.purdue.edu/~alamgrp/papers-pdf/2007_nair_TED_Design_NanoBiosensor.pdf

[6] Off-State Degradation in Drain-Extended NMOS Transistors: Interface Damage and Correlation to...D Varghese, H Kufluoglu, V Reddy, H Shichijo, ... MA Alam - ElectronDevices, IEEE Transactions on, 2007
http://cobweb.ecn.purdue.edu/~alamgrp/papers-pdf/2007_varghese_TED_offstate_DENMOS.pdf

[7] Scaling Limits of Double-Gate and Surround-Gate Z-RAM Cells. NZ Butt, MA Alam - Electron Devices, IEEE Transactions on, 2007
http://cobweb.ecn.purdue.edu/%7Ealamgrp/papers-pdf/2007_nauman_TED_SI_ZRAM_Scaling.pdf

[8] Soft Error Trends and New Physical Model for Ionizing Dose Effects in Double Gate Z-RAM Cell. NZ Butt, PD Yoder, MA Alam - Nuclear Science, IEEE Transactions on, 2007
http://cobweb.ecn.purdue.edu/%7Ealamgrp/papers-pdf/2007_butt_TNS_softerror_ZRAM.pdf

[9] An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function. Q Chen, A Guha, K Roy - Proceedings of the 20th International Conference on VLSI, 2007
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4092110

[10] Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias. S Mukhopadhyay, H Mahmoodi, K Roy - Computer-Aided Design of Integrated Circuits and Systems, January 2008
http://ieeexplore.ieee.org/iel5/43/4407552/04358298.pdf?isnumber=4407552&arnumber=4358298

[11] Accurate Modeling and Analysis of Currents in Trapezoidal FinFET Devices. R Rao, A Bansal, J Kim, K Roy, CT Chuang - SOI Conference, 2007 IEEE International, 2007
http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4357818&arnumber=4357845&count=80&index=26

[12] Body Thickness Optimization and Sensitivity Analysis for High Performance FinFETs. D Lekshmanan, A Bansal, K Roy - Device Research Conference, 2007 65th Annual, 2007.
http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4373617&arnumber=4373664&count=135&index=46

[13] FinFET Based SRAM Design for Low Standby Power Application. T Cakici, K Kim, K Roy - Proceedings of the 8th International Symposium on Quality, 2007
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4149023

[14] FinFET SRAM: Optimizing Silicon Fin Thickness and Fin Ratio to Improve Stability at iso Area. D Lekshmanan, A Bansal, K Roy - Custom Integrated Circuits Conference, 2007. CICC 2007. IEEE, 2007 IEEE 2007 Custom Integrated Circuits Conference (CICC)
http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4405667&arnumber=4405809&count=200&index=141

[15] The Effect of Process Variation On Device Temperature In finFET Circuits - JH Choi, J Murthy, K Roy - Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM, 2007
http://www.gigascale.org/pubs/1191/p747-choi.pdf

[16] Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices. A Datta, A Goel, RT Cakici, H Mahmoodi, D Lekshmanan, K Roy. - Computer-Aided Design of Integrated Circuits and Systems, ., 2007
http://ieeexplore.ieee.org/iel5/43/4351994/04352003.pdf?arnumber=4352003

[17] Low-Power Process-Variation Tolerant Arithmetic Units Using Input-Based Elastic Clocking. D Mohapatra, G Karakonstantis, K Roy - International symposium on Low power electronics and design, 2007
http://www.gigascale.org/pubs/1082/ErrorResilientExecutionUnits.pdf

[18] Fine-Grained Redundancy in Adders. P Ndai, SL Lu, D Somesekhar, K Roy - . the 8th International Symposium on Quality Electronic Design, 2007
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4149054

[19] Design Methodology to Trade Off Power, Output Quality and Error Resiliency: Application to Color. G Karakonstantis, N Banerjee, K Roy, C Chakrabarti - . International Conference on Computer Aided Design, 2007. ICCAD 2007. IEEE/ACM International., 2007
http://portal.acm.org/citation.cfm?id=1326073.1326114&coll=&dl=

[20] A Process Variation Aware Low Power Synthesis Methodology for Fixed-Point FIR Filters. N Banerjee, JH Choi, K Roy - International symposium on Low power electronics and design, 2007.
http://www.gigascale.org/pubs/1071/LowPowerProcessTolerantFilterDesign.pdf

[21] Process Variation Tolerant Low Power DCT Architecture. N Banerjee, G Karakonstantis, K Roy - Proceedings of the conference on Design, automation and test ., 2007
http://www.gigascale.org/pubs/995/ProcessTolerantLowPowerDCT.pdf

[22] Exploring High-Speed Low-Power Hybrid Arithmetic Units at Scaled Supply and Adaptive Clock- . S Ghosh, K Roy - . of the 2008 conference on Asia and South Pacific design., 2008
http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4483913&arnumber=4484029&count=157&index=115

[23] A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking. S Ghosh, P Ndai, K Roy - Design, Automation and Test in Europe, 2008. DATE 2008
http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4484624&arnumber=4484707&count=312&index=82