Increasing leakage current, especially the subthreshold leakage due to non-scaling of the subthreshold slope is one of the most serious impediments to further scaling of classical MOSFETs. Tunnel FETs (TFET) with sub-60mV/decade subthreshold slope are attractive alternatives for the sub-45nm and lower gate lengths. Various techniques for optimization of T-FET performance, like bandgap engineering including hetero-junction source [1] and gate dielectric scaling [2] are proposed in the literature. In this work we explore for the first time, the design space for n-channel T-FETs with gate lengths below 22nm using extensive device simulations. We show that the ITRS requirements for HP and LSTP [3] can be achieved using a SiGe-source device by an optimum choice of gate dielectric thickness and Ge fraction in Si_1-γGeγ.

The authors would like to acknowledge Synopsys for educational licenses of Sentaurus and Medici used in this work.

For more information on this work, please refer to the paper presented at the 66th Device Research Conference: http://drc.ee.psu.edu/abstracts/vnikam-20080319-235.pdf