CORES IP

Understanding the Fundamentals of PCI Express
PCI Express® - or PCIe® - is a high performance, high bandwidth serial communications interconnect standard that has been devised by the Peripheral Component Interconnect Special Interest Group (PCI-SIG) to replace bus-based communication architectures, such as PCI, PCI Extended (PCI-X) and the accelerated graphics port (AGP). The objective of this white paper is to equip the reader with a broad understanding of PCI Express and the design challenges essential to successful PCIe implementation.

DDR SDRAM: A Low Cost, Yet Increasingly Complex Off-Chip Memory Solution for SoCs
Almost everyone knows that the bulk of DRAMs produced end up in desktop and laptop computers just like the one used to write the whitepaper. In fact, approximately 90% of all DRAMs are used in computers – leaving the remaining 10% as square pegs pounded into round holes when used as off-chip memory for SoCs. As the number of SoC designs requiring an interface to external memory increases, the modern DDRn SDRAM memory interface (DDR, DDR2, DDR3) offers security of supply, high storage capacity, low cost and reasonable channel bandwidth, but comes with an awkward interface and complicated controller issues.

How A Complete IP Solution Speeds Time-to-Market and Reduces Risk for 10 Gigabit Ethernet Applications
This paper discusses the merits of IP for the growing 10G Ethernet market and introduces Synopsys' complete DesignWare® 10G Ethernet IP solution in the context of the technology and the target applications. It mentions the market growth trends and highlights typical application areas for 10G Ethernet.

Benefits and Applications of the Wireless USB WHCI Host and Dual-Role Device
The intent of this article is to provide an overview of the newly introduced features for the DesignWare Cores WiUSB Controller (DWC_uwb) core. In this article, customers would gain insights into the technical details of the new features as well as the benefits these new features bring to the applications. Furthermore, the technical advantages of the DWC_uwb core are explained to provide customers a better understanding of the core design.

Agere/Synopsys: Integrating a PCI Express Digital IP Core into a Gigabit Ethernet Controller
A Gigabit Ethernet controller incorporating a PCI Express interface takes advantage of the high-throughput, low latency capabilities of PCI Express to deliver true gigabit performance. These enhanced capabilities allow for optimal sizing and utilization of on-chip memory, providing significant power and area savings. This paper discusses the integration and system verification challenges encountered when integrating a PCI Express digital IP core into a Gigabit Ethernet design. Techniques for configuration of the PCI Express IP are presented that achieve the lowest power, lowest latency and smallest memory size, as well as optimal system performance.

Favorable Economics Will Drive Rapid Adoption of Certified Wireless USB
Consumers have embraced the convenience of each wireless revolution – from landlines to cell phones, wired networks to Wi-Fi networks. Our need for wireless connectivity, familiarity with the USB standard and the favorable economics of Certified Wireless USB, will ensure it is a success. Certified Wireless USB technology from the USB Implementers Forum (USB-IF) will be adopted more rapidly than Wi-Fi, and even outpace the take-up of wired Hi-Speed USB 2.0 devices. This paper provides an up-to-date report on the status of Certified Wireless USB technology. It explores the favorable economic factors and technology benefits that Synopsys believes will drive rapid adoption of this new standard.