A key component of the DesignWare DDR3/2 PHY is the extensive in system data training/calibration capability in order to maximize the overall timing budget and improve system reliability. The DesignWare DDR3/2 PHY contains calibration circuits for read data eye training (optimizes and maintains the optimal DQS offset into the center of the read data eye), write data eye training (optimizes and maintains the optimal DQS offset into the center of the write data eye), per-bit deskew training (minimizes bit to bit timing skew for reads and writes independently), DDR3 write leveling, and DDR3 read leveling.

DesignWare DDR3/2 PHY Datasheet
 

• Highlights
• Products
• Downloads and Documentation

• When combined with a DesignWare DDR memory or protocol controller and verification IP, Synopsys provides a complete DDR3/2 interface IP solution
• Scalable architecture that supports the speed range from DDR2-667 up to DDR3-2133
• Support for DDR3L (1.35V DDR3)
• Delivery of product as a hardened Mixed-Signal macrocell components allows precise control of timing critical delay and skew paths
• Low latency
• PHY Utility Bock (PUB) included as a soft IP utility that includes control features, such as write leveling and data eye training, and provides support for production testing of the DDR3/2 PHY (available with select PHYs)
• DFI 2.1 compliant interface (optional)
• Configurable external data bus widths between 8 and 64 bits in 8-bit increments plus ECC
• Permits operating with DDR3/2 SDRAMs using data widths narrower than the compiled data width
• Support for 1 to 4 memory ranks
• DDR3/2 PHY-Controller interface runs at 4:1 mode (width ratio of application bus to memory data bus), simplifying core logic timing constraints
• Includes the PLL and all timing circuits necessary to meet timing specifications
• Write leveling timing circuits to compensate address and control versus data delays
• Write and read bit timing circuits compensate per-bit delay skew of individual data bits within each data byte
• Locally calibrated master and slave timing circuits minimize OCV and ACLV effects, and accommodate voltage or temperature change induced timing drift
• Area optimized I/O
• 6 layers of metal
• 35um I/O pitch for 65nm
• 30um pitch for 40nm
• Staggered I/O supported
• Supports CUP (Circuit Under Pad) and (Bond Over Active)
• Supports flip chip and wire bond
• I/O retention mode (available with select PHYs)
• Maintains I/O drive state during VDD power down
• Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self refresh mode
• Advanced testability
• At-speed loopback testing on both the address and data channels
• Delay line oscillator test mode
• MUX-scan ATPG
• Optional DDR signal integrity service is available to assist customers with the integration of the PHY into their SoC, package and printed circuit board environments

DDR3/2 PHY - CHRT 65G25 V2	STARs	Subscribe
DDR3/2 PHY - IBM 65G25	STARs	Subscribe
DDR3/2 PHY - IBM 90G25	STARs	Subscribe
DDR3/2 PHY - TSMC 40G18	STARs	Subscribe
DDR3/2 PHY - TSMC 40LP25	STARs	Subscribe
DDR3/2 PHY - TSMC 45LP25	STARs	Subscribe
DDR3/2 PHY - TSMC 55GP25	STARs	Subscribe
DDR3/2 PHY - TSMC 65GP25	STARs	Subscribe
DDR3/2 PHY - UMC 65SP25	STARs	Subscribe

Description	DDR3/2 PHY - CHRT 65G25 V2
Name	dwc_ddr3_ddr2_phy_chrt65g25_v2
Version	2.00a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	Implementation IP
Documentation	Show Documents... Hide Documents... Application Note DesignWare Cores DDR3/2 SDRAM PHY Application Note Overview Databook DesignWare Cores DDR3/2 SDRAM PHY Databook Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	dwc_ddr3_ddr2_phy_chrt65g25_v2
Description	DDR3/2 PHY - IBM 65G25
Name	dwc_ddr3_ddr2_phy_cp65g25_1600
Version	1.10a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	Implementation IP
Documentation	Show Documents... Hide Documents... Application Note DesignWare Cores DDR3/2 SDRAM PHY Application Note Overview Databook DesignWare Cores DDR3/2 SDRAM PHY Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	dwc_ddr3_ddr2_phy_cp65g25_1600
Description	DDR3/2 PHY - IBM 90G25
Name	dwc_ddr3_ddr2_phy_ibm90g25
Version	1.00a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	Implementation IP
Documentation	Show Documents... Hide Documents... Application Note DesignWare Cores DDR3/2 SDRAM PHY Application Note Overview Databook DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	dwc_ddr3_ddr2_phy_ibm90g25
Description	DDR3/2 PHY - TSMC 40G18
Name	dwc_ddr3_ddr2_phy_tsmc40g18
Version	2.11a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	Implementation IP
Documentation	Show Documents... Hide Documents... Application Note DesignWare Cores DDR3/2 SDRAM PHY Databooks DesignWare Cores DDR3/2 PHY Utility Block Databook, v2.01a DesignWare Cores DDR3/2 SDRAM PHY Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	dwc_ddr3_ddr2_phy_tsmc40g18
Description	DDR3/2 PHY - TSMC 40LP25
Name	dwc_ddr3_ddr2_phy_tsmc40lp25
Version	2.10a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	Implementation IP
Documentation	Show Documents... Hide Documents... Application Note DesignWare Cores DDR3/2 SDRAM PHY Databooks DesignWare Cores DDR3/2 PHY Utility Block Databook, v2.01a DesignWare Cores DDR3/2 SDRAM PHY Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	dwc_ddr3_ddr2_phy_tsmc40lp25
Description	DDR3/2 PHY - TSMC 45LP25
Name	dwc_ddr3_ddr2_phy_tsmc45lp25
Version	1.10a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	Implementation IP
Documentation	Show Documents... Hide Documents... Application Note DesignWare Cores DDR3/2 SDRAM PHY Databook DesignWare Cores DDR3/2 SDRAM PHY Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY
Download	dwc_ddr3_ddr2_phy_tsmc45lp25
Description	DDR3/2 PHY - TSMC 55GP25
Name	dwc_ddr3_ddr2_phy_tsmc55gp25
Version	1.20a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	Implementation IP
Documentation	Show Documents... Hide Documents... Application Note DesignWare Cores DDR3/2 SDRAM PHY Databook DesignWare Cores DDR3/2 SDRAM PHY Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	dwc_ddr3_ddr2_phy_tsmc55gp25
Description	DDR3/2 PHY - TSMC 65GP25
Name	dwc_ddr3_ddr2_phy_tsmc65gp25
Version	2.10a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	Implementation IP
Documentation	Show Documents... Hide Documents... Application Note DesignWare Cores DDR3/2 SDRAM PHY Databooks DesignWare Cores DDR3/2 PHY Utility Block Databook, v2.01a DesignWare Cores DDR3/2 SDRAM PHY Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	dwc_ddr3_ddr2_phy_tsmc65gp25
Description	DDR3/2 PHY - UMC 65SP25
Name	dwc_ddr3_ddr2_phy_umc65sp25
Version	2.00a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	Implementation IP
Documentation	Show Documents... Hide Documents... Application Note DesignWare Cores DDR3/2 SDRAM PHY Databook DesignWare Cores DDR3/2 SDRAM PHY Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY
Download	dwc_ddr3_ddr2_phy_umc65sp25