| User Papers |
| TA1 - Applied Verification Techniques Using Transactors and Dynamic Randomization |
Application of Dynamic Random Sequencing in Augmenting Constrained Randomization for System Verification
Author(s): Pei-hsiu Suen, Alicia Strang, Robert Lee [QLogic Corporation] |
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Designing a Reusable Transactor using Transactor Callback Methods - A Case Study
Author(s): John Zook [StarGen Inc] Jason Chen [Synopsys Inc] |
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Method for Data Link Layer and Physical Layer Error Insertion
Author(s): Jim Sweeten [StarGen Inc] Anthony Ezell [Synopsys Inc] |
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| TA2 - Low Power Design |
Fight the Power - Power Reduction Ideas for ASIC Designers and Tool Providers
Author(s): David Bond, Serag GadelRab, David Reynolds [Tundra Semiconductor] |
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Power Integrity for a Low Power Mixed Signal Consumer Market SoC
Author(s): Badhri Uppiliappan [Analog Devices] |
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Rapid Deployment of an IEM Enabled ARM1176JZFS with Galaxy Power
Author(s): John Biggs, Peter Uttley [ARM Ltd] |
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| TA3 - Effective Design And Methodology Techniques |
Does HDL Code Quality Matter Anymore? (or Has Design Compiler Made Hardware Engineers Obsolete?)
Author(s): Brian Kane [Cognio Inc] |
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The Living Hell of Identifiers and define_name_rules
Author(s): Maurice Kinney [IBM Microelectronics] Ray Yock, Denise Powell [Synopsys Inc] |
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| TA4 - Clock And Power Network Design for Complex SoCs |
Analyzing Clock Trees (Best First-Time Presenter, Technical Committee Award Honorable Mention)
Author(s): Jeff Shabel [QUALCOMM Inc] |
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Complex SOC Clocking: Design, Constraints, Strategies and Pitfalls
Author(s): Bart MacLean [Intellon Canada Inc] |
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Power Network Synthesis and Analysis with JupiterXT and PrimePower
Author(s): Thomas Roche, Glen Macon [Analog Devices] |
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| TB1 - Application of the Reference Verification Methodology (RVM) |
Building Constrained-Random Techniques, Functional Coverage, Scoreboard and the Complete RVM Environment Above the Existing Legacy Verification Environment
Author(s): Virendra Jaiswal, Jitendra Puri [nSys Design Systems Pvt] Fabian Delguste [Synopsys SARL Ltd] |
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Optimizing the Development of a Random-Constrained Self-Checking Verification Environment by Using a Supported Methodology (1st Place - Best Paper, Technical Committee Award Honorable Mention)
Author(s): Nancy Pratt [IBM Systems & Technology Group] Quinn Canfield [Synopsys Inc] |
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Reusable Register Structure for the Reference Verification Methodology
Author(s): Andrew Elms [Tundra Semiconductor Corporation] |
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| TB2 - Floorplanning |
A Technology Independent Floorplanning Flow Utilizing Design Compiler, JupiterXT and IC Compiler
Author(s): Stefan Creaser, Philip Watson [ARM Ltd] Stephen Edgeworth, Jason Jackson, Antony Newbold [Synopsys UK] |
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Flipchip I/O Floorplanning
Author(s): Jason Werkheiser [Agere Systems], Tom Concannon [Synopsys Inc.] |
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Power Plan Design Techniques for 0.13u Designs
Author(s): Srini Burugu, Sumeer Arya, Steve Doan [Synopsys Inc] Sameer Nayar [PLX Technologies] |
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| TB3 - Design Flow And Methodology |
AMBA DesignWare® and coreAssembler Simplify the Design Flow and Improve Design Timing for STMicroelectronics Digital Radio Controller & Audio Decoder
Author(s): Sam Bordbar [Synopsys Italia SRL] Mauro Bosco [STMicroelectronics] Andreas Vielhaber [Synopsys GmbH] |
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Applying the Reuse Model to EDA Tool Flows - A DC to Astro Flow using Object-Oriented Perl and XML
Author(s): Kevin Skey [The MITRE Corporation] |
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Managing Scan Test Time using DFT Compiler, TetraMAX, and VTRAN
Author(s): Sverre Wichlund [Nordic Semiconductor ASA] |
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| TC1 - Use Of Assertions in Simulation And Formal Verification |
Leveraging Assertion Based Verification by using Magellan (Technical Committee Award)
Author(s): Jacob Andersen, Peter Jensen [SyoSil Consulting] |
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Solving Verilog X-Issues by Sequentially Comparing a Design with Itself - You'll never trust unix diff again (3rd Place - Best Paper)
Author(s): Mike Turpin [ARM Ltd] |
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| TC2 - System Level Modeling & Physical Design Flow |
Doing Your Due Diligence Physically
Author(s): Kenneth Chang [iVivity Inc] |
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Using System Level Modeling to Enhance SoC Verification Lead-Time
Author(s): Remi Francard, Vincent L Homme Desages, Harpreet Singh [STMicroelectronics] Fabian Delguste [Synopsys SARL] Holger Keding [Synopsys GmbH] |
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| TC3 - Front-End Design |
RDL - Register Description Language
Author(s): Julian Gorfajn [Maxtor Corporation] |
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Using Synthesis in High Performance Microprocessor Design
Author(s): Sunita Adluri [Intel Corporation] |
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| TC4 - Verification With SystemVerilog |
A Unique Functional Coverage Flow using SystemVerilog and NTB (2nd Place - Best Paper)
Author(s): Richard Raimi [ARM Ltd] Dennis Strouphauer [Synopsys Inc] |
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Object Oriented Testbench Development with VeraHVL and SystemVerilog Assertions (SVA)
Author(s): Glenn Dunlap [Sigmatel] |