Overview
The PCIe form factor HAPS-A31 is a high-performance rapid prototyping board containing one Altera Stratix III and one Arria-GX device. Utilizing the high-performance, high-density Stratix III EP3SL340 device makes these rapid prototyping boards ideal for DSP intensive applications such as base stations, network infrastructure, and advanced imaging equipment. A single HAPS-A31 board can accommodate up to 2 million ASIC gates. For larger capacity designs, the HAPS–A31 can be expanded by connecting additional motherboards and/or daughter boards using the HapsTrak standard. The HapsTrak standard assures compatibility between the HAPS-A31 and other HAPS motherboards and daughter boards, allowing designers the flexibility to implement various design applications and configurations.
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- Features
- Single Altera Stratix III device, EP3SL340 in an F1760 package yyUp to 2 million ASIC gates on one HAPS-A31 board
- Signaling rate: 1 Gbps LVDS, 600 Mbps single-ended
- 714 I/Os in 6 HapsTrak II connectors
- 60 general purpose I/Os
- 1 GByte DDR3 SDRAM SO-DIMM module
- 1 programmable clock generator
- on-board or external oscillator
- 2 pairs of differential and 2 single-ended internal clocks
- 2 single-ended external clock outputs
- 1 direct external clock output
- 1 fixed 100 MHz reference clock
- 6 I/O voltage regions for each HapsTrak connector, adjustable to 2.5, 1.8, 1.5 or 1.2 V
- Configuration via JTAG cable, HapsTrak CDE or PCI Express
- Fast data transfer via the 4-lane PCI Express bus
- On-board temperature and voltage monitor
- Length matched, 50-Ohm impedance traces to all HapsTrak connectors
- Setup via PCI Express or USB – no DIP switches, no jumpers
Figure 1: On-board functions of the HAPS-A31 board
On-board functions
The I/O signals in the HapsTrak II connectors on the HAPS-A31 board are compatible with user I/O and HAPS daughter boards and/or Motherboards.
The tight physical connection between the FPGA and the DDR3 SDRAM module provides high-speed memory access.
The programmable clock generator can be used for clocking the users design.
A supervisor device monitors temperature and voltage, and controls configuration and data transfer to the Stratix device.
User I/O
User I/O is available in 6 HapsTrak II connectors. The connectors can be used either for attaching daughter boards or for creating inter-FPGA buses between multiple motherboards. All connections are made to matching connectors on the bottom of the board making it possible to stack two or more motherboards on top of each other.
Each HapsTrak II connector has 119 pins reserved for user I/Os; 118 of these pins support differential signaling. The I/O voltage is set individually for each connector to 2.5, 1.8, 1.5, or 1.2V. If other I/O voltages are required, the power can be sourced from the bottom of the HapsTrak II connectors.
Power
All necessary voltages are generated on-board from a single 12V power source. DC/DC converters generate the I/O voltages for the HapsTrak II connectors.
Configuration
The Altera Stratix FPGA is configured via either the PCI Express bus, a JTAG cable, or the HapsTrak CDE bus.
Board Supervision
The HAPS-A31 conducts self-tests that check the status of the board, including short circuits and open circuits for every signal in the HapsTrak II connectors. Errors are indicated by on-board LEDs.
Remote Use
Built-in functions provide support for remote set up, monitoring, and reconfiguration of a HAPS system -simplifying support of dispersed hardware and software design teams.
Figure 2: Rapid high level synthesis for optimized HAPS-A31 implementation
Algorithmic prototyping solution
Synopsys’ Synphony HLS software provides a fast and efficient way to get algorithm designs into the HAPS-A31. Synphony HLS software allows designers to quickly create and debug high level models of their design, then from a single model they can automatically synthesize architecture and device optimized RTL in addition to optimized ASIC implementations for exploration. The software enables design teams to rapidly prototype their algorithms for high speed system validation and early software development and leverage the results for ASIC verification and implementation.