PrimeTime 2010 Scales Timing Analysis Beyond 500 Million Instances
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PrimeTime HyperScale technology extends PrimeTime
static timing analysis to support designs beyond 500
million instances. It delivers between 5 and 10X better
runtimes for the full chip timing analysis and 5 to 10X
smaller memory footprint compared with classic flat analysis.
Antun Domic, senior vice president and general manager,
Implementation Group, Synopsys |
HyperScale technology works with existing features like SI analysis, Advanced OCV for variation,
and threaded multicore analysis to enable design teams increase their STA productivity and overall
chip timing closure turn-around-time. HyperScale technology fits with today’s physical implementation
flows where designs are implemented in blocks and then assembled into the chip level for final timing closure and signoff.
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