At DAC in June 2010, industry experts at AMD, LSI Corporation, Renesas Electronics, Samsung, STMicroelectronics and Texas Instruments presented to over 200 Synopsys guests. The presenters explained how they relied on In-design physical verification with IC Validator for improved productivity and faster design closure.
John Chilton, Moderator, Sr. VP of Marketing & Corporate Development, Synopsys -- Antun Domic, Sr. VP and General Manager of the Implementation Business Unit, Synopsys -- Davide Casalotto, Design Methodologies Project Leader, STMicroelectronics -- Ed Roseboom, Member, Technical Staff, AMD -- Kyle Peavy, Physical Design Engineer, Texas Instruments -- Koki Tsurusaki, Senior Engineer, Back-end Design Technology Development Dept., Platform Integration Division , Renesas Electronics -- Tom Luczejko, Director, Principal Engineer, LSI Corporation -- Harpreet Gill Sr. Engineering Manager, System LSI SoC R&D, Samsung Electronics

ARM Cortex-A9 MPCore Multi-core Processor Hierarchical Implementation with IC Compiler Learn how ARM utilized IC Compiler’s concurrent hierarchical design for multi-core implementation, driving better performance as well as better throughput.
Philip Watson, Implementation Environment Program Manager

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Automatic Block Size Reduction with IC Compiler MinChip Technology IC Compiler reduces runtime and memory while delivering hand-craft-quality macro placement, MinChip die size reduction, clock tree synthesis, skew optimization, clock-gate merging, and more. STMicroelectronics achieved a huge reduction in die-size with a runtime of only 4 to 6 hours!
Naveen Raina, Technical Specialist

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IC Compiler: Routing and Design for Manufacturability (DFM) IC Compiler uses concurrent optimization techniques to simultaneously consider the impact of manufacturing rules, timing, and other design goals for high QoR and improved manufacturability.
Raj Varada, Principal Engineer

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Concurrent Hierarchical Design with IC Compiler, Real Life Application on Mobile Multi-Media Processor IC Compiler offers the industry’s first concurrent hierarchical design system that delivers a high degree of automation combined with high-quality optimization. Learn more about the results Toshiba achieved with the latest advances in IC Compiler.
Mutsunori Igarashi, Chief Specialist, Design Methodology Development

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Few easy ways for getting the best PrimeTime performance and achieving faster sign-off analysis.
Karen Linser, staff applications engineer in Synopsys’ Implementation Group

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Design Compiler Graphical, the newest member of the Design Compiler product family, creates a better starting point for physical implementation and can shave weeks off your design schedule.

Manufacturing process variations can introduce small delays that adversely affect critical design paths, leading to circuit failures. Dr. T.W. Williams introduces technology developed at Synopsys to detect defects creating these delays, thereby increasing the test quality.