Synopsys’ unified solution for custom and cell-based design and verification provides a comprehensive, highly integrated suite of tools for advanced-node mixed-signal SoC design. The high degree of integration and interoperability shortens time-to-tapeout and improves design quality.
Synopsys

The Galaxy Implementation Platform provides seamless integration between the IC Compiler physical implementation and Galaxy Custom Designer custom implementation solutions, accelerating the design development cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development while maintaining design data integrity.
Synopsys

Multi-Source CTS delivers the ideal hybrid solution for designers seeking the best of conventional CTS and pure clock mesh. IC Compiler Multi-Source CTS provides better high-speed performance and OCV tolerance than conventional CTS and is more tolerant of complex floorplans and provides more flexibility for clock gating depth than pure clock mesh.
Harvey Toyama, Synopsys Implementation Group

HSPICE Precision Parallel technology is a new multicore transient simulation extension to HSPICE for both pre- and post-layout of complex analog circuits such as PLLs, ADCs, DACs, SERDES, and other full mixed-signal circuits. HPP addresses the traditional bottleneck in accelerating SPICE on multicore CPUs with new algorithms that enable a larger percentage of the simulation to be parallelized, with no compromise in golden HSPICE accuracy. Additionally, efficient memory management allows simulation of post-layout circuits larger than 10 million elements.
Robert Daniels, Sr. Staff Engineer, Synopsys Inc.; Harald Von Sosen, Principal Engineer, Synopsys Inc.; Hany Elhak, Product Marketing Manager, Synopsys Inc.

SmartDRD is a new, innovative technology built into Galaxy Custom Designer™ Layout Editor (LE) for interactive DRC violation visualization, detection and correction, commonly known as design-rule-driven (DRD) editing
Synopsys

When combining intellectual property (IP) blocks from various sources, the chip-level implementation teams may not have the detailed IP knowledge required to develop timing constraints for the IP.
Synopsys

Synopsys’ RTL synthesis solution has been the No. 1 choice of ASIC designers worldwide since 1987. Countless numbers of chips have been designed using Synopsys’ synthesis solution and over 60 semiconductor and library vendors offer hundreds of libraries supporting Synopsys synthesis.
Synopsys inc.;