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Achieving Rapid Verification Convergence of ARM® AMBA® 4 ACE™ Designs using Discovery™ VIP
Overview of challenges of verifying a coherent design. Shows how the features and architecture of Synopsys’ new Discovery VIP helps overcome these challenges to simplify verification of ACE design.
Abhijeet Khopkar, R&D Manager, Synopsys; Neill Mullinger, Group Marketing Manager, Synopsys
May 08, 2012 | | | Get the Most from Your HSPICE Simulation
Unleash the power of HSPICE simulations with useful tips and tricks to reduce simulation time without compromising HSPICE’s gold-standard accuracy.
Szekit Chan, HSPICE Staff Corporate Applications Engineer, Synopsys
Nov 30, 2011 | | | Understand and Avoid Electromigration (EM) & IR-drop Effects in Custom IP Blocks
Learn how process technology & changing design styles increase the impact of EM & IR-drop effects on the performance/reliability of AMS, memory & custom digital IP blocks at 28nm and below.
Bradley Geden, Solution Architect, Synopsys
Oct 26, 2011 | | | VCS Productivity Technologies - Reducing the Growing Verification Cycle
Learn about VCS’ most recent technology advancements and new features enabling productivity in the following key areas: performance and capacity, verification planning, coverage and debug.
Michael Sanie, Director of Product Marketing, Synopsys; Shekhar Mahatme, Senior Staff Application Engineer (Verification Methodology), Synopsys
Sep 21, 2011 | | | New Advancements in Verification Methodology (VMM and UVM)
Learn about the latest improvements in verification performance and productivity including the new Synopsys features offered in support of standards-based SystemVerilog verification methodologies.
Adiel Khan, Senior Staff Engineer, Synopsys; Kiran Maiya, Corporate Application Engineer, Synopsys; Michael Sanie,
Director of Product Marketing, Synopsys
Jul 28, 2011 | | | Advanced Regression and Analysis for Mixed-Signal Verification Using CustomExplorer Ultra
Learn how CustomExplorer Ultra enables high verification productivity for complex SoCs using advanced strategies that surpass traditional verification approaches.
Duncan McDonald, Product Marketing Manager, Synopsys; Dwayne Holst, Corporate Applications Engineer, Synopsys
May 11, 2011 | | | Accurate Jitter and Noise Analysis Using HSPICE Transient Noise Techniques
Learn about new time-domain noise analysis approaches available in HSPICE, and how transient noise analysis can verify critical timing and noise performance characteristics.
Scott Wedge, Sr. Staff Engineer, Synopsys
May 04, 2011 | | | New Levels of Productivity for USB 3.0 Verification
This Webinar will highlight recent advances in Synopsys verification IP technology that build on a pure SystemVerilog implementation.
Bernie Delay, Director R&D, Verification Goup, Synopsys; Steve McMaster, R&D Engineer, Verifiction Group, Synopsys;
Zongyao Wen, R&D Manager, Verification Group, Synopsys
Apr 21, 2011 | | | CustomSim and VCS Extend Digital Verification Techniques to Mixed-Signal Designs
Use CustomSim and VCS to create reusable mixed-signal verification environments that enable analog assertions, analog verification planning, analog stimulus and analog self-checkers to find bugs related to analog and digital interfaces sooner.
Bradley Geden, CustomSim Product Marketing Manager, Synopsys; Fabian Delguste, Principle Corporate Application Engineer, Synopsys
Jan 26, 2011 | | | Using ESP-CV for Faster Redundancy Verification in Memory Designs
ESP-CV performs functional equivalence checks between a Verilog design and its transistor level implementation. The designs may be described as Verilog behavioral models, RTL, or gates, and a SPICE netlist. The new redundancy verification features in ESP-CV provide the ability to quickly and efficiently verify memory designs implemented with row and column redundancy.
Dave Hedges , CAE, Implementation Group, Synopsys;
Clay McDonald, R&D Manager, Implementation Group, Synopsys
Jan 19, 2011 | | | Advances in Circuit Analysis with the Custom Designer Simulation and Analysis Environment
Learn how to efficiently use Custom Designer's SAE in conjunction with HSPICE and Custom WaveView to analyze a design across process and parameter variations.
Kristin Beggs, R&D Engineer, Synopsys
Oct 27, 2010 | | | Accelerate Analog Simulation with HSPICE Precision Parallel Technology
Learn how HSPICE Precision Parallel technology accelerates verification of analog/mixed-signal circuits up to 7X on 8 cores while maintaining gold-standard accuracy.
Hany Elhak, Product Marketing Manager, Synopsys; Fredrik Ivarsson, Corporate Applications Engineer, Synopsys
Oct 20, 2010 | | | VCS Coverage Driven Verification
As the challenge of verification continues to grow, engineers are increasingly turning to verification planning, advanced coverage techniques and unique coverage technologies to optimize the tracking of verification progress and significantly improve the quality of their designs. In this webinar, you will learn about the latest advances in verification planning, coverage and coverage methodology. In addition, you will also discover some of the unique advantages of using VCS, including VCS’ Echo testbench coverage convergence technology.
Albert Chiang, Product Marketing Manager, Synopsys; Paul Graykowski Applications Engineer, Synopsys; Jean Fong Applications Consultant, Synopsys; Vernon Lee, Principle Engineer, Synopsys; and Rahul Dani, R&D Engineer, Synopsys
Sep 08, 2010 | | | Multi-Gigabit Signal Integrity Analysis with HSPICE
Learn about HSPICE capabilities for modeling high-frequency channel components, and high-performance simulation and analysis features for characterizing multi-gigabit links.
Scott Wedge, Ph.D, Sr. Staff Engineer, Synopsys
Aug 18, 2010 | | | Find Electrical Violations Before Tapeout with CustomSim Circuit Check
Learn how customers are using CustomSim Circuit Check to analyze designs with hundreds of millions of transistors to catch electrical violations before tapeout.
Bradley Geden, Product Marketing Manager, Synopsys
Jul 21, 2010 | | | Unleash the Power of Hybrid Formal Verification for Advanced Bug Hunting
Successful, cost-effective verificaiton of a design requires quick and early bug detection. In this webinar, you will learn how Synopsys' Magellan hybrid technology speeds up bug hunting and provides unique value to design and verification teams.
Krishna Balachandran, Director of Marketing Synopsys; Mandar Munishwar, Corporate Applications Engineer, Synopsys; Xiaolin Chen, Corporate Applications Engineer, Synopsys; Dan Benua, Principal Engineer, Synopsys
May 04, 2010 | | | Static Verification Throughout the Low Power Design Flow
Learn how MVRC and Formality tools complement each other to statically verify your design from RTL to transistors.
Krishna Balachandran, Director of Product Marketing, Synopsys; Prapanna Tiwari, Staff CAE, Synopsys; Bob Hatt, Staff CAE, Synopsys
Apr 28, 2010 | | | Verify Digitally-Assisted Analog Circuits with CustomSim Fast Transient Analysis
Learn how the CustomSim high-capacity, fast transient analysis solution can help you increase design confidence and reduce project development time.
Bradley Geden, Product Marketing Manager, Synopsys; Tom Hsieh, AMS CAE, Synopsys
Mar 25, 2010 | | | Transaction-level Debug Using VCS
In this webinar, you will learn about the basics of transaction-level modeling, why it is needed, how it integrates with an RTL design and how the Synopsys VCS functional verification solution supports both transaction-level and pin-level debug in its Discovery Visualization Environment (DVE).
Albert Chiang, Product Marketing Manager, Synopsys; Yasser Khan, Sr. Corporate Applications Engineer, Synopsys; Dr. Bassam Tabbara, Senior Staff R&D Engineer, Synopsys; Brett Kobernat, Applications Consultant, Synopsys
Jan 27, 2010 | | | Efficient & Accurate Memory Timing & Power Analysis using CustomSim
With the growing complexity of device models and the increasing impact on timing and power measurements from physical layout effects, accurate memory verification within a reasonable timeframe is a necessity. This webinar highlihgts memory verification methodologies and how choosing the right methodology enables memory designers to produce the highest-accuracy timing and power measurements in the shortest turnaround time. Learn how Synopsys’ CustomSim™ solution is being used today for accurate and efficient memory timing and power analysis.
Bradley Geden, Product Marketing Manager, Synopsys
Dec 16, 2009 | | | CustomSim for Memory Timing & Power Analysis
This webinar highlights memory verification methodologies and how choosing the right methodology enables memory designers to produce the highest-accuracy timing and power measurements in the shortest turnaround time.
Bradley Geden, Product Marketing Manager, Synopsys
Dec 15, 2009 | | | The Recipe for Successful Formal Verification: Proper Constraining of Your Design
Learn all about constraints and how their proper specification and use will help you quickly achieve your verification goals. Synopsys’ Magellan hybrid formal tool helps detect and debug over-constraining of your formal setup, thereby increasing your confidence in your formal verification results.
Krishna Balachandran, Director of Marketing, Synopsys; Mandar Munishwar, Corporate Applications Engineer, Synopsys; Xiaolin Chen, Corporate Applications Engineer, Synopsys; and Dan Benua, Principal Engineer, Synopsys
Nov 11, 2009 | | | Achieving 2x Verification Speedup with VCS Multicore
Learn how VCS multicore technology allows users to reduce verification time for long-running tests by leveraging their multicore computing infrastructure. We cover VCS multicore technology’s two flexible use models: application-level parallelism (ALP) and design-level parallelism (DLP).
Chiang, Product Marketing Manager, Synopsys; Usha Gaira, Corporate Applications Engineer, Synopsys; Amitabh Chand, Corporate Applications Engineering Manager, Synopsys; and Jatinder Goraya, Research and Development Engineer, Synopsys
Oct 27, 2009 | | | VMM: The Next Generation - Delivering Enhanced Ease-of-use, TLM 2.0 Support and Robust Block-to-top Reuse
VMM base classes, VMM Applications and VMM-LP are deployed worldwide to address the toughest verification challenges. In this webinar, our experts cover new enhancements like TLM 2.0 support, improved block-to-top reuse heirarchical phasing and additional ease-of-use deployment features.
Albert Chiang, Product Marketing Manager, Synopsys; Yassine Eben Amine, Applications Consultant, Synopsys; and Kiran Maiya, Senior Corporate Applications Engineer, Synopsys
Oct 13, 2009 | | | Extraction Techniques to Accelerate High-Capacity Simulation
StarRC can enable up to 10x speed-up in simulation runtime while preserving golden accuracy. In this webinar our experts explain innovative techniques to boost simulation performance and capacity for your custom digital, memory or AMS designs.
Synopsys
Sep 22, 2009 | | | Combining Formal Verification with Simulation: The Best of Both Worlds
Learn how Synopsys' Magellan seamlessly integrates formal verification with simulation to achieve complete verification of today's complex designs.
Krishna Balachandran, Director of Verifiation Marketing, Synopsys; Xiaolin Chen, Corporate Applications Engineer, Synopsys; Mandar Munishwar Corporate Applications Engineer, Synopsys; Dan Benua, Principal Engineer, Synopsys
Aug 25, 2009 | | | Everything You Always Wanted to Know About Low Power Verification
An understanding of the impact on verification from the deployment of low power design techniques is key to successful verification. Learn why verification has changed for low power designs and how Synopsys' VCS with MVSIM and MVRC comprehensively and accurately meet these challenges.
Krishna Balachandran, Director of Low Power Verification Marketing, Synopsys; Prapanna Tiwari, Corporate Applications Engineering Manager, Synopsys
Aug 11, 2009 | | | A Structured Methodology for Verifying Low Power Designs
In this webinar, we focus on the bug types that are new to low power design and introduce a structured and reusable methodology highlighting VMM extensions to base classes for low power that can be quickly used to replicate an efficient verification environment for low power designs.
Krishna Balachandran, Director of Low Power Verification Marketing, Synopsys; Srikanth Jadcherla, Group Director of R&D, Synopsys; Janick Bergeron, Synopsys Fellow, Synopsys
Aug 11, 2009 | | | The VCS Discovery Visualization Environment (DVE)
The Discovery Visualization Environment (DVE) offers unified debug and analysis of Verilog, VHDL, C/C++/SystemC, SystemVerilog Assertion/Design/Testbench and analog waveforms. Learn about DVE features such as coverage, planning, and interactive debug of a VMM environment with SystemC.
Albert Chiang, Technical Marketing Manager, Synopsys; Yasser Khan, Applications Engineer, Synopsys; Don Walters, R&D Manager, Synopsys;
Apr 30, 2009 | | | HSPICE StatEye – ISI Predictions Made Easy
Are your high-speed serial link simulations taking too long? Want to speed up your eye diagram generation and ISI predictions by 100X? If so, learn how to speed up high-speed serial link analyses and get the most out of the statistical eye diagram capability in HSPICE.
Christopher Labrecque, Marketing Manager, Synopsys
Apr 29, 2009 | | | Increase Design Confidence with CustomSim
Learn how CustomSim addresses verification challenges for a diverse array of functional blocks, including custom digital, analog and memory designs. Learn how to take advantage of multi-threading capabilities to achieve an additional 4x performance improvement.
Synopsys
Apr 28, 2009 | | | Leveraging Constraint Solver Technology in VCS
Learn how VCS constraint solver technology can increase design quality while accelerating verification and minimizing cost. In addition, the speakers address debugging and profiling of constraints and discuss a few "tips and tricks" that help simplify constraint writing.
Synopsys
Jan 29, 2009 | | | Verifying Complex Power-managed Designs
An overview of approaches that address the difficult task of verifying low power designs.
Synopsys
Dec 18, 2008 | | | Leakage Mitigation in ARM Processor-based Systems
Leakage mitigation techniques such as power gating, state retention and dynamic threshold scaling have been shown to significantly reduce standby power consumption.
Alan Gibbons, Principal Engineer, Synopsys; John Biggs, Consultant Engineer, ARM
Dec 18, 2007 | | | Robust SI Analysis of a DDR2 Interface with HSPICE
For years designers around the world have trusted HSPICE for their signal integrity simulation needs
Dr. Scott Wedge, Senior Staff Engineer, Synopsys; Ted Mido, Senior Staff Engineer, Synopsys
Feb 13, 2007 | | | Predicting PLL Phase Noise & Jitter with HSPICE RF
Due to today’s ever increasing data rates, phase noise and jitter specifications are now critical aspects of modern phase-locked loop design.
Dr. Scott Wedge, Senior Staff Engineer, Synopsys
Jan 03, 2007 | | |
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