Synopsys demonstrates the DesignWare SATA 6 Gb/s AHCI Host controller and PHY implemented on Synopsys' HAPS FPGA-Based Prototyping Solution interoperating with a commercially available SATA 6 Gb/s device.
Scott Knowlton, SATA Product Marketing Manager and Mat Loikkanen, SATA R&D, Synopsys

Utilizing the LeCroy's protocol analyzer, exerciser and test suite, Synopsys demonstrates PCI Express 3.0 transactions through the DesignWare PCI Express 3.0 IP implemented on the Synopsys HAPS FPGA prototyping system.
Scott Knowlton, PCIe Product Marketing Manager, Torrey Lewis, PCIe R&D, Synopsys

Demonstrated USB 3.0 interoperability with a USB 3.0 Certification Gold Tree including all USB traffic types
Eric Huang, Product Manager, Synopsys

DisplayLink shows Synopsys USB 3.0 Device, PHY, and HDMI IP in Mass Production chips in real products
Eric Huang, Product Manager, Synopsys and Theo Goguely, Product Manager, DisplayLink

Super fast SuperSpeed USB 3.0 demonstrated in a real system
Eric Huang, Product Manager, Synopsys

Does proven IP have more value?
Eric Huang, Product Manager, Synopsys and Theo Goguely, Product Manager, DisplayLink

This demonstration will feature the post-silicon interactive automation capabilities of the DesignWare STAR Silicon Browser, which utilizes the DesignWare STAR Memory System's embedded test & repair IP solution.
Yervant Zorian, Chief Architect, Synopsys, Gevorg Torjyan, R&D Engineer, Synopsys

Synopsys demonstrates proven system-level interoperability utilizing Synopsys' DesignWare MIPI CSI-2 and DSI host controller as well as the DesignWare MIPI D-PHY IP solution
Hezi Saar, Product Marketing Manager, DesignWare MIPI IP; Miguel Falcao Sousa, R&D Manager, Solutions Group

This video demonstrates the fully characterized, silicon-proven capabilities of the DesignWare MIPI M-PHY IP solution, highlighting its silicon performance as well as its electrical characteristics, which exceed target specifications.
Celio Albuquerque, R&D Manager, DesignWare MIPI PHY IP

This video provides a high level view of popular MIPI protocols and helps you get up to speed with latest mobile market innovations. We will also introduce IP solutions that can help you differentiate your products in the mobile market space.
Hezi Saar, Product Marketing Manager, DesignWare MIPI IP

With the release of the IEEE 802.1 specifications for Audio Video Bridging (AVB) designers can now include this functionality in their designs with the DesignWare® Ethernet QOS core. This demonstration will show how a Ethernet design can easily be configured to support AVB capable networks.
John Swanson, Senior Manager, Synopsys

See how Synopsys’ DesignWare Audio IP delivers superb audio quality, featuring a full set of audio functions needed by most of today’s consumer electronic devices. Synopsys also showcases the true Hi-Fi audio quality delivered by the DesignWare Audio Codec with dynamic range exceeding 96dB, while keeping the power consumption at minimum levels.
João Risques, Product Manager for DesignWare Audio and Video AFE IP, Synopsys

Learn how DisplayLink uses Synopsys DesignWare SuperSpeed USB 3.0 and HDMI IP to create their next-generation USB graphics technology.
Eric Huang Product Marketing Manager, USB Digital Controller and VIP; Jason Slaughter, Director of Marketing, DisplayLink

Discover how DisplayLink leverages adaptive compression over USB 3.0 to create a smooth, full screen video and graphic experience with low latency.
Eric Huang Product Marketing Manager, USB Digital Controller and VIP; Jason Slaughter, Director of Marketing, DisplayLink

In this video, you will discover how to quickly migrate an existing USB 2.0 design to USB 3.0. By leveraging Synopsys’ silicon-proven, complete DesignWare SuperSpeed USB 3.0 IP solution with MCCI’s software stack, you can lower integration risk and improve time-to-market of your next-generation USB 3.0 design.
Eric Huang Product Marketing Manager, USB Digital Controllers and VIP; Terry Moore CEO, MCCI

In this video, you will see how the Synopsys DesignWare® SuperSpeed USB 3.0 controller and PHY IP enable faster performance speeds, reaching up to 335 MB/s. Using MCCI’s USB 3.0 software stack on a Synopsys HAPS platform, the DesignWare SuperSpeed USB 3.0 IP solution offers USB 3.0 speeds in both 2.0 and 3.0 modes.
Eric Huang Product Marketing Manager, USB Digital Controller and VIP

This demonstration features LeCroy’s Summit T3-16 Protocol Analyzer, Summit Z3-16 Protocol Exerciser and the Summit Z3-16 Test Platform to test a PCI Express 3.0-based design for compliance to the PCI Express 3.0 specification. The design-under-test (DUT) utilizes the DesignWare® IP for PCI Express 3.0.
Featuring: John Wiedemeier, Product Manager, LeCroy; Scott Knowlton, Product Marketing Manager, Synopsys

Utilizing a DUT that implements the DesignWare IP for PCI Express 3.0, this demonstration features Agilent’s complete test solution for PCI Express 3.0 and the Digital Test Console to check for compliance to the PCI Express 3.0 specification.
Featuring: Yenyi Fu, Product Manager, Agilent; Scott Knowlton, Product Marketing Manager, Synopsys

By using DDR Hard PHY IP, you achieve: quicker integration, easier timing closure, better performance and less silicon area. With a hard PHY, all the IP is supplied by one IP vendor and includes I/Os. Hard PHYs have lower jitter, better duty cycle, an overall superior clock strategy and use identical circuits for every bit of the parallel DDR interface reducing skew. In addition, hard PHYs implemented in test chips are equivalent to the customer's PHY where as soft PHYs are different GDSII every time.
Synopsys Super Stars

This demonstration shows proven interoperability of Synopsys' DesignWare USB 3.0 PHY with the DesignWare USB 3.0 host and device controllers implemented in FPGAs. View a high-definition video running at hundreds of megabytes per second.
Gervais Fong Product Marketing Manager, USB PHY IP

Live from DesignCon 2010, see how the DesignWare DDR3/2 IP enables automatic timing compensation for voltage and temperature changes, per bit deskew adjustments in the datapath, and on-chip capabilities for measuring write and read data eyes.
Graham Allan, Product Marketing Manager, Memory Interface IP; Vishal Thareja, Test Engineer

DisplayLink demonstrates how it uses DesignWare SuperSpeed USB 3.0 and HDMI IP to show full HD resolution over USB 3.0 by taking video directly out of USB 3.0 on the PC, convert it to HDMI and display it directly to a high-resolution monitor.
Gervais Fong, Product Marketing Manager, USB PHY IP Dennis Crespo, Vice President of Marketing, DisplayLink

Synopsys shows how fixed video and audio patterns are transmitted by the DesignWare HDMI TX controller and PHY. See the image quality improve as resolution of video test pattern is increased from 480p to 720p to 1080p, 60 Hz frame formats. Also see the EDID info collected by TX Controller/PHY Display Data Channel (DDC) from the sink device (DTV) to support negotiation and find the best supported color format and frame rate.
Manmeet Walia, Product Manager for Mixed-Signal PHY IP, Synopsys

This demonstration will showcase Synopsys' HAPS platform with a DesignWare SuperSpeed USB 3.0 core and PHY running MCCI's USB 3.0 software stack. Designers will learn how they can start their design process for mobile phone and multimedia portable USB products with working drivers.
Eric Huang, Product Marketing Manager, USB Digital Cores; Terry Moore, CEO, MCCI

See Synopsys and MCCI demonstrate how music can be synchronized in a matter of seconds in a USB 3.0 media player compared to minutes in a USB 2.0 media player. The demonstration consists of the Synopsys DesignWare® SuperSpeed USB Digital Controller and MCCI SuperSpeed USB Software on an FPGA hardware platform.
Eric Huang Product Marketing Manager, USB Digital Controllers and VIP; Terry Moore CEO, MCCI

TI demonstrates SuperSpeed USB interoperability and USB 2.0 backward compatibility. The demo showcases TI's TUSB80x0 Hub and TUSB9260 SATA bridge controller with the Synopsys DesignWare SuperSpeed USB 3.0 IP
Eric Huang, Product Marketing Manager, USB Digital Controllers and VIP; Scott Kim, Business Development Manager, Connectivity Solutions, TI

See high-definition video using the DesignWare® SuperSpeed USB 3.0 xHCI Host and Device Controller implemented in an FPGA. This demonstration shows a 1080p, 30 frames per second video streaming from a standard PC running on a Linux operating system with a SuperSpeed USB 3.0 xHCI Host Stack, into mass storage device.
Eric Huang, Product Marketing Manager, USB Digital

See a live demonstration of the 45-nm DesignWare PHY and controller IP for PCI Express® 2.0 operating in a single-lane configuration at 5 GT/s. The demonstration verifies 5 GT/s operation using the PCI® Tree software and executes Reads and Writes between the demo hardware and a PC to show throughput performance levels.
Scott Knowlton, Sr. Produt Marketing Manager, Synopsys

See real SuperSpeed USB 3.0 data transfers of Synopsys' DesignWare® SuperSpeed USB 3.0 xHCI Host, Hub and Device digital controllers in a single demonstration. In this video, Synopsys shows interoperability between the DesignWare SuperSpeed USB 3.0 controllers and a USB 3.0 mass storage device, USB 2.0 flash controller and USB 1.1 mouse.
Eric Huang, Product Marketing Manager, USB Digital Controllers and VIP

See how Synopsys demonstrates proven interoperability with the complete DesignWare® SATA IP solution, consisting of digital controllers, mixed-signal PHY and Verification IP. This video consists of hardware demonstrations for the DesignWare SATA AHCI Host, Device, PHY and 6 Gb/s IP solutions.
Mat Loikkanen Sr. R&D Engineer, Synopsys; Mick Posner Sr. Product Marketing Manager, Synopsys

Join us in the Synopsys lab to see proven interoperability between the Texas Instrument’s USB 3.0 transceiver and the Synopsys DesignWare USB 3.0 host and device controller implemented in FPGAs. View a high-definition video running at hundreds of megabytes per second.
Eric Huang, Product Marketing Manager, USB Digital Controllers and VIP; Scott Kim, Business Development Manager, Connectivity Solutions, TI

See how Global Unichip (GUC) utilized Synopsys' silicon-proven DesignWare® SATA IP in its Solid State Device (SSD) GP5080 platform to demonstrate a netbook boot-up time of less than half a minute. The hardware platform consists of a high-performance 32-bit ARM7 processor, SATA 3Gb/s interface, SLC/MLC NAND Flash management of up to 4 channels, 8 banks with ECC.
Kurt Huang, Director of Marketing, Global Unichip Corp.

Join Synopsys in our lab to see actual USB 3.0 data transfer utilizing the DesignWare Superspeed USB Host and Device Controllers implemented in an FPGA. This demonstration shows a 1080p, 30 frames per second video, streaming from the device into the host with a measured throughput of 460 MB/s utilizing the Lecroy CATC analyzer.
Eric Huang, Product Marketing Manager, USB Digital Controllers and VIP

See firsthand the test equipment and custom boards developed and used by Synopsys to verify our DDR IP. Witness full speed write and read data eyes, at speed functionality testing, duty cycle and phase error tests and jitter analysis results.
Graham Allan, Product Marketing Manager, DDR IP

Join Synopsys in our lab to see how we deliver a compliant, robust PCI Express 2.0 PHY and enable visibility into the link performance through unique on-chip diagnostics.
Navraj Nandra, Marketing Director MSIP

The video will take you through our silicon verification board set up, show the unique tunability feature and highlight the extensive characterization process of the USB 2.0 nanoPHY.
Gervais Fong, Product Marketing Manager, USB PHY IP