PCI Express® - or PCIe® - is a high performance, high bandwidth serial communications interconnect standard that has been devised by the Peripheral Component Interconnect Special Interest Group (PCI-SIG) to replace bus-based communication architectures, such as PCI, PCI Extended (PCI-X) and the accelerated graphics port (AGP).
Scott Knowlton, Product Marketing Manager, Synopsys

Almost everyone knows that the bulk of DRAMs produced end up in desktop and laptop computers just like the one used to write the whitepaper. In fact, approximately 90% of all DRAMs are used in computers – leaving the remaining 10% as square pegs pounded into round holes when used as off-chip memory for SoCs. As the number of SoC designs requiring an interface to external memory increases, the modern DDRn SDRAM memory interface (DDR, DDR2, DDR3) offers security of supply, high storage capacity, low cost and reasonable channel bandwidth, but comes with an awkward interface and complicated controller issues.
Graham Allan, Senior Product Manager, Synopsys

This paper discusses the merits of IP for the growing 10G Ethernet market and introduces Synopsys' complete DesignWare® 10G Ethernet IP solution in the context of the technology and the target applications. It mentions the market growth trends and highlights typical application areas for 10G Ethernet.
Geetha R. Arun, Synopsys

Today’s IP choices for the Universal Serial Bus (USB) cover many different types of interfaces for use in a wide variety of applications—including portable consumer products. Power consumption and small form factors are thus key issues. SoC designers must also consider new requirements imposed by smaller technology nodes, especially for the USB PHY. This paper provides insights into dealing with these issues and profiles the USB IP choices available from Synopsys.
Gervais Fong, Product Marketing Manager,Synopsys; Eric Huang, Product Marketing Manager,Synopsys

To successfully develop an AMBA™ 3 AXI™ protocol-based design in the shortest time requires a comprehensive set of synthesizable IP, verification IP and an automated method to assemble the entire SoC subsystem. The AMBA 3 Advanced eXtensible Interface (AXI) protocol builds on the benefits of the AMBA 2.0 standard offering greater performance and flexibility.
Mick Posner, Synopsys, Inc

The need for higher performance applications is driving the requirement for a new age of on-chip communication infrastructure. Increasing the clock frequency no longer addresses this higher performance requirement, as the bottleneck is inherent in the existing bus infrastructure.
Mick Posner—Synopsys, Darrin Mossor—Synopsys

PCI Express® - or PCIe® - is a high performance, high bandwidth serial communications interconnect standard that has been devised by the Peripheral Component Interconnect Special Interest Group (PCI-SIG) to replace bus-based communication architectures, such as PCI, PCI Extended (PCI-X) and the accelerated graphics port (AGP).
Scott Knowlton, Product Marketing Manager, Synopsys

Almost everyone knows that the bulk of DRAMs produced end up in desktop and laptop computers just like the one used to write the whitepaper. In fact, approximately 90% of all DRAMs are used in computers – leaving the remaining 10% as square pegs pounded into round holes when used as off-chip memory for SoCs. As the number of SoC designs requiring an interface to external memory increases, the modern DDRn SDRAM memory interface (DDR, DDR2, DDR3) offers security of supply, high storage capacity, low cost and reasonable channel bandwidth, but comes with an awkward interface and complicated controller issues.
Graham Allan, Senior Product Manager, Synopsys

Today’s IP choices for the Universal Serial Bus (USB) cover many different types of interfaces for use in a wide variety of applications—including portable consumer products. Power consumption and small form factors are thus key issues. SoC designers must also consider new requirements imposed by smaller technology nodes, especially for the USB PHY. This paper provides insights into dealing with these issues and profiles the USB IP choices available from Synopsys.
Gervais Fong, Product Marketing Manager Eric Huang, Product Marketing Manager

PCI Express® - or PCIe® - is a high performance, high bandwidth serial communications interconnect standard that has been devised by the Peripheral Component Interconnect Special Interest Group (PCI-SIG) to replace bus-based communication architectures, such as PCI, PCI Extended (PCI-X) and the accelerated graphics port (AGP).
Scott Knowlton, Product Marketing Manager, Synopsys

Almost everyone knows that the bulk of DRAMs produced end up in desktop and laptop computers just like the one used to write the whitepaper. In fact, approximately 90% of all DRAMs are used in computers – leaving the remaining 10% as square pegs pounded into round holes when used as off-chip memory for SoCs. As the number of SoC designs requiring an interface to external memory increases, the modern DDRn SDRAM memory interface (DDR, DDR2, DDR3) offers security of supply, high storage capacity, low cost and reasonable channel bandwidth, but comes with an awkward interface and complicated controller issues.
Graham Allan, Senior Product Manager, Synopsys

This paper discusses the merits of IP for the growing 10G Ethernet market and introduces Synopsys' complete DesignWare® 10G Ethernet IP solution in the context of the technology and the target applications. It mentions the market growth trends and highlights typical application areas for 10G Ethernet.
Geetha R. Arun, Synopsys

PCI Express® - or PCIe® - is a high performance, high bandwidth serial communications interconnect standard that has been devised by the Peripheral Component Interconnect Special Interest Group (PCI-SIG) to replace bus-based communication architectures, such as PCI, PCI Extended (PCI-X) and the accelerated graphics port (AGP).
Scott Knowlton, Product Marketing Manager, Synopsys

Almost everyone knows that the bulk of DRAMs produced end up in desktop and laptop computers just like the one used to write the whitepaper. In fact, approximately 90% of all DRAMs are used in computers – leaving the remaining 10% as square pegs pounded into round holes when used as off-chip memory for SoCs. As the number of SoC designs requiring an interface to external memory increases, the modern DDRn SDRAM memory interface (DDR, DDR2, DDR3) offers security of supply, high storage capacity, low cost and reasonable channel bandwidth, but comes with an awkward interface and complicated controller issues.
Graham Allan, Senior Product Manager, Synopsys

Today’s IP choices for the Universal Serial Bus (USB) cover many different types of interfaces for use in a wide variety of applications—including portable consumer products. Power consumption and small form factors are thus key issues. SoC designers must also consider new requirements imposed by smaller technology nodes, especially for the USB PHY. This paper provides insights into dealing with these issues and profiles the USB IP choices available from Synopsys.
Gervais Fong, Product Marketing Manager, Synopsys; Eric Huang, Product Marketing Manager, Synopsys

Today’s IP choices for the Universal Serial Bus (USB) cover many different types of interfaces for use in a wide variety of applications—including portable consumer products. Power consumption and small form factors are thus key issues. SoC designers must also consider new requirements imposed by smaller technology nodes, especially for the USB PHY. This paper provides insights into dealing with these issues and profiles the USB IP choices available from Synopsys.
Gervais Fong, Product Marketing Manager, Synopsys Eric Huang, Product Marketing Manager, Synopsys

Almost everyone knows that the bulk of DRAMs produced end up in desktop and laptop computers just like the one used to write the whitepaper. In fact, approximately 90% of all DRAMs are used in computers – leaving the remaining 10% as square pegs pounded into round holes when used as off-chip memory for SoCs. As the number of SoC designs requiring an interface to external memory increases, the modern DDRn SDRAM memory interface (DDR, DDR2, DDR3) offers security of supply, high storage capacity, low cost and reasonable channel bandwidth, but comes with an awkward interface and complicated controller issues.
Graham Allan, Senior Product Manager, Synopsys

This document summarizes two classes of RTL coding guidelines for the synthesis of datapaths: Guidelines that help achieve functional correctness and intended behavior of arithmetic expressions in RTL code. Guidelines that help datapath synthesis to achieve best possible QoR (Quality of Results).
Reto Zimmermann – Synopsys