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USB IP Blog: To USB or Not to USB
Covering the latest trends and topics in USB IP.
Eric Huang
The Eyes Have it: A Mixed-Signal IP Blog
This blog discusses all things related to mixed-signal PHY IP such as the latest trends, design challenges and anything that may be controversial.
Navraj Nandra
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SYNOPSYS CLOSES VIRAGE LOGIC ACQUISITION
Extends interface and analog IP portfolio: adds embedded memories, logic libraries and more
NEW PRESS RELEASE
Synopsys DesignWare SATA IP Enables First-Pass Silicon Success for Global Unichip Corporation
DesignWare MIPI M-PHY IP
Address Demand for Higher Throughput in LTE and WiMAX Mobile Devices
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MEDIA ADVISORY/ALERT: Synopsys Showcases DesignWare IP Solutions for PCI....
Synopsys DesignWare SATA IP Enables First-Pass Silicon Success for Global....
Synopsys Announces Immediate Availability of DesignWare MIPI M-PHY IP in 40-nm....
Synopsys Launches DesignWare USB Software Alliance Program
Synopsys and GLOBALFOUNDRIES to Develop DesignWare Interface PHY IP for....
Synopsys First to Deliver High-Performance Audio IP in 40-nm and 55-nm Process....
Open-Silicon Integrates 50 DesignWare Interface and Analog IP Products with 100....
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Chip Design: A New Generation of Audio/Video Coming to a Network Near You
Electronics Weekly: Synopsys says it is vital to test IP for SoCs
Chip Design: Does Wireless Communication Drive the Evolution of Data Converters?
DAC.com: Tested and Tried: The Right Way to Evaluate Your IP Vendor
ChipEstimate.com: Using PCI Express for I/O Virtualization
Tech Talks on EDA Confidential: Is there such a thing as analog IP?
EDA DesignLine: Integrating analog video interface IP into SoCs delivers superb image quality (Part II)
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Blogs
USB IP Blog: To USB or Not to USB
The Eyes Have it: A Mixed-Signal IP Blog
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Success Stories
Fairchild Achieves First-Pass Silicon Success Using DesignWare USB 2.0 nanoPHY IP and Meets Project Schedule for Next-Generation USB 2.0 Transceiver SoC
eRide Achieves First-Pass Silicon Success for High-Sensitivity GPS SoC with DesignWare IP for the AMBA Interconnect
AMIMON Achieves First-Pass Silicon Success for High-Definition Wireless Video and Audio SoC with DesignWare DDR2 IP
Zenverge Achieves High-Performance Requirements for Advanced Media Transcoder SoC with DesignWare DDR IP
K-Micro Meets High-Performance Requirements for Home Networking SoCs with DesignWare Data Converter IP
Netronome Selects Synopsys’ DesignWare DDR Controller and PHY IP for High-Performance Network Processor SoC
Ambarella Delivers Innovative Hybrid Camera SoC Platform with High-Quality DesignWare USB and Ethernet IP
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White Papers
Sweet Sounding SoCs: Why Analog Audio IP Lowers Costs and Sounds Better than Digital PWM
Understanding Clock Jitter Effects on Data Converter Performance and How to Minimize Them at the System Level?
Ethernet Quality-of-Service: New IEEE Specifications Driving a New Generation of Network Products
Debugging SuperSpeed USB Software Using Virtual Prototypes
High Definition Video AFE: Far Beyond the ADC
Reverse Process Migration from 65nm to 130nm in Under Three Months
Improving I/O Virtualization Performance with PCI Express
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Webinars
Analog IP into Digital SoC for Broadband Communication
The Next Generation of Ethernet
Understanding PCI Express 3.0
Shaping the Perfect Audio Codec
DesignWare IP for AMBA 3 AXI On-Chip Bus
Mixed-Signal PHY IP
Understanding HDMI
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Videos
Synopsys and LeCroy Showcase PCI Express® 3.0 Interoperability at PCI-SIG 2010
Synopsys and Agilent Enable PCI Express 3.0 Ecosystem at PCI-SIG 2010
Make it EASY with Synopsys DesignWare DDR HARD PHY IP
Synopsys Demonstrates SuperSpeed USB 3.0 Interoperability
DesignWare DDR3/2 IP Demo at 1600 Mbps
DisplayLink Streams Uncompressed HD 1080p Video Using Synopsys’ USB 3.0 IP
Silicon-proven DesignWare® HDMI TX Controller and PHY IP on Synopsys’ HAPS-51 Platform
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DesignWare Technical Bulletin - Q2-09
DesignWare Technical Bulletin - Q3-08
DesignWare Technical Bulletin - Q2-08
DesignWare Technical Bulletin - Q1-08
DesignWare Technical Bulletin - Q4-07
DesignWare Technical Bulletin - Q3-07
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