ISQED 2010
March 22-24
DoubleTree Hotel
San Jose, CA
Tuesday March 23
LUNCHEON SPEECH — Test of the Future: Some Thoughts for the Next Decade
12NOON to 1:30PM
Room: Oak/Fir
Speaker: Dr. Antun Domic, Sr. Vice President and General Manager
Over the last 40 years, test has moved from being a fab tool to being a design tool, and has become an integral part of the design flow. This move has allowed better (QOR), cheaper (COR), and faster (TTR) test. As the vanguards of the semiconductor industry approach the 32-nanometer node and start planning the jump to the 22-nanometer node, a number of fundamental challenges are emerging, which force a thorough rethinking of the role of test. Like drugs, which often have counter-indications and side effects, even nanometer design and manufacturing are not immune to drawbacks. This requires that test assume an equal station to nanometer design and manufacturing, is accounted for by them, and inter-operates thoroughly with them. Both implementation and yield management tools may feed test with the design and manufacturing-related information it needs to keep problems manageable, while guaranteeing the desired quality and cost of results. At the same time, test can feed implementation and manufacturing with a great deal of information, which can help identify, locate, fix and/or prevent yield issues. In this keynote, Dr. Domic will describe how design, manufacturing, and test can join forces, and “collaborate” to battle the nanometer challenges.
SESSION 3A — Variability: Design, Test, and Characterization
4:00PM
Room: Monterey
3A.2 Is Built-In Logic Redundancy Ready for Prime Time?
Speaker: Chris Allsup, Technical Marketing Manager
With each new process generation, it becomes ever more challenging to maintain high yields of integrated circuits. Progressively lower yields potentially undermine the profits of semiconductor companies across all industry segments. Embedding redundant logic into designs can improve product yields, but is this economically viable for most systems-on-chip? This paper attempts to answer this fundamental question. After describing an example architecture for built-in logic redundancy (BILR), we examine precisely how the BILR design and test parameters affect the area overhead, test execution time and yield of the redundant system. After conveying the cost model, we present analysis results showing that redundancy could be cost-effective, depending on a number of cost infrastructure variables that include the parameters of the BILR system itself.
EMBEDDED SESSION 3D — Poster Papers
3:45 to 5:45PM
Room: Donner
3D.5 Constraint Analysis and Debugging for Multi-Million Instance SoC Designs
R&D Team: Long Fei, Loa Mize, Cho Moon, Bill Mullen, and Sonia Singhal
Timing constraints are used by implementation tools in all design stages in modern design flows. With the growing complexity of design and constraints, it is increasingly challenging to identify, diagnose, and fix constraint problems. In this paper, we present the technology of an interactive constraint debugger that automatically checks constraint problems, and gives context-sensitive diagnosis and fix suggestions. Our extensive user feedback shows that the tool significantly improves designer productivity.
Wednesday March 24
SESSION 4D — Embedded Tutorial
10:30AM to 12NOON
Room: San Jose
4D: A Scalable Methodology for Analog and Mixed-Signal Verification
Speaker: Shyam Rapaka, R&D Engineer and Tapan Halder, R&D Director
Traditional verification approaches for analog & mixed-signal designs do not scale well with increasing design complexity and product functionality. Full chip verification in the presence of analog components can be very slow, tedious, and difficult to maintain. In this tutorial, we focus on a scalable methodology for analog & mixed-signal verification that leverages advanced techniques used for verification of digital designs. Behavioral modeling using Verilog-AMS and SystemVerilog constructs will be presented. This tutorial addresses the several challenging issues that present road blocks for verification closure, and presents a methodology that promotes reuse and easy to maintain verification environment. Various strategies will be explored, for both top-down and bottom-up approaches, to develop a framework that can be shared across design teams, design stages, and product cycles.
SESSION 6A — Clocking Strategy for Modern Low Power Multi-Core and Structured ASICs
3:45 to 5:45PM
Room: Monterey
6A.1 A Revisit to the Primal-Dual Based Clock Skew Scheduling Algorithm
Speaker: Min Ni, R&D Engineer
Clock skew scheduling is a useful sequential circuit optimization method. The run time efficiency of this problem becomes crucial if it must be repeated iteratively in a higher level optimization. The widely recognized Burns' algorithm proposed to solve this problem suffers from high runtime complexity, which makes it unsuitable to be deployed in iterative optimization loops. This algorithm is based on the general concept of primal-dual optimization. In this paper, we demonstrate that a more efficient approach to the clock skew scheduling problem can be developed by designing a new algorithm using the same primal-dual optimization concept. The basic idea of the algorithm is to avoid creating new admissible graph and recalculating theta values for each iteration of the primal-dual optimization. The asymptotic runtime efficiency of our algorithm is of O(|V||E|+|V|log|V|), which is improved from O(|V|^2|E|) thanks to the heap data structure used in our proposed algorithm. The experimental results show that our algorithm is on average 95 times faster than Burns' implementation. In a best case, we can observe as much as 189 times speedup.