| Time | Description |
| 8:30-9:30 | Registration and Breakfast |
| 9:30-10:00 | Welcome and Introduction: Mike Bartley, SNUG UK Technical Chair - Test and Verification Solutions Ltd.
Synopsys Update: Peter Bell, Senior Technical Manager - Synopsys UK |
| 10:00-10:30 | Break |
| 10:30-12:00 | A1 Tutorial & Combo Session
FPGA Implementation and FPGA-based Prototyping I | A2 User Session
Back End Implementation I | A3 User Session
Design for Test I | A4 Tutorial & User Session
Verification I | A5 Tutorial & User Session
AMS / Full Custom Design I |
|
| 12:00-13:15 | Lunch |
| 13:15-14:45 | B1 Tutorials
FPGA Implementation and FPGA-based Prototyping II | B2 Tutorial
Back End Implementation II | B3 User Session & Tutorial
Design for Test II | B4 User Session
Verification II | B5 Tutorials
AMS / Full Custom Design II |
| 14:45-15:00 | Break |
| 15:00-16:45 | C1 Tutorials
FPGA Implementation and FPGA-based Prototyping III | C2 User Session & Tutorials
Low-Power | C3 User Session
Design Verification | C4 User Session & Tutorial
IP and Systems | C5 User Session & Tutorial
AMS / Full Custom Design III |
| 16:45-18:00 | |