SNUG Singapore 2010 Conference at a Glance

Grand Hyatt Singapore
Hibiscus Room, Level 3

Time	Description
8:00-8:50	Registration and Breakfast
8:50-9:00	MC Introduction
9:00-10:00	Welcome and Synopsys Keynote: Mr Don Chan, VP, Corporate Application Engineering, Implementation Group, Synopsys Inc.
10:00-10:10	Event Introduction

10:10-10:40	User Paper 1: Effective Design Partitioning & Floorplanning for Complex SoC
10:40-11:00	Tea Break & Demo
11:00-11:30	User Paper 2: PrimeTime Advanced OCV – Another Way to Performance Confidence
11:30-12:00	User Paper 3: Hitting Bull's Eye Using HSIM in Nanometer Design
12:00-13:00	Lunch
13:00-13:35	Low Power Forum	Tutorial: LYNX *Seating limited to 20
13:35-14:05	User Paper 4: DFT for a Low Pin Count SoC
14:05-14:35	User Paper 5: Clocking Methodology for Performance Verification in SoC Design
14:35-14:55	Tea Break & Demo
14:55-15:25	User Paper 6: Using StarRC for Accurate Post-Layout SPICE Netlist Extraction	Tutorial: PrimeTime How to improve runtime *Seating limited to 20
15:25-15:55	User Paper 7: Custom ICC Flow For High Speed Long Channel Repeaters Insertion In SOC Design	Tutorial: Design Compiler 2010.03 Update *Seating limited to 20
15:55-16:25	User Paper 8: Making DFM Sense In Your Design
16:25-16:35	Guess the Best Speaker
16:35-17:05	Tutorial : Feasibility for IC Implementation
17:05-17:20	Best Paper Awards & Lucky Draw!

* Registration is 1st-come-1st serve basis only