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SNUG Boston 

Boston Marriott Newton Hotel 

Newton, MA
September 6, 2012

SNUG Boston is your opportunity to learn, share and engage with your fellow Synopsys technology users. In addition to an exceptional technical program that will give you practical information you can apply to your current project or use to jump-start your next design, SNUG also offers plenty of opportunities to share experiences, network with other users and meet with Synopsys experts to learn about the newest products and preview future technology direction.

 

SNUG Boston Proceedings
Check out the SNUG Boston proceedings library to locate user papers or tutorials that contain solutions you can apply to your own design challenges.


1st Place - Best Paper Block Level Scan Insertion and Layered Approach to Transition ATPG Vector Generation
Zahi Abuhamdeh, Vincent D'Alessandro [Silicon DFx, Inc.], Ramon Zuniga, Wayne Fang [ClariPhy Communications, Inc.]
PaperPresentation


2nd Place - Best Paper Deployment of Full Custom Created Timing Shell Methodology to Hand-Off Macros from CD to ICC
Michael Wagner [Lantiq D GmbH], Oliver Baer, Kurt Haun [Synopsys GmbH]
PaperPresentation


3rd Place - Best Paper Improving Functional Gate Level Simulation Performance - A Case Study
Joe Tompkins [Cavium Networks], Prathamesh Joshi [Synopsys Inc.]
PaperPresentation


Technical Committee Award Honorable Mention The Impulse Response - "Fingerprint" for SERDES Channel Characterization
Johann Nittmann, Frank Corcoran [Cavium Networks]
PaperPresentation


ProceedingsDownload 2011 proceedings
PAPERS (9 MB) PRESENTATIONS (11 MB) TUTORIALS (35 MB)


 
New to SNUG, the Designer Community Expo featured over 20 companies, spanning 6 design communities, exhibiting products integrated with Synopsys solutions.

SNUG thanks the members of the Technical Committee who volunteer their time and expertise to ensure SNUG’s technical quality, local perspective and value to the users of Synopsys tools and technology.

User Technical Chairperson
Jay Wasserman, Analog Devices, Inc.

Members
Al Czamara, Test Evolution
Al Conti, The MITRE Corp.
Alex Tetelbaum, LSI
Andy Copperhall, ARCH Design
Avishek Panigrahi, Xilinx
Brian Kane, Northrop Grumman Corp.
Chris Kiegle, IBM
Dinesh Tyagi, Innovative Logic Inc.
Don Mills, LCDM Engineering
Frank Szorc, Linear Technology
Heath Chambers, HMC Design Verification, Inc.
John Dickol, Samsung
John Wei, Alchip Technologies
Jonathan Wolfe, Samsung
Jonah Probell, Arteris
Leah Clark, Broadcom Corp.
Mark Sprague, AMD
Mike Bartley, Test and Verification Solutions, Ltd.
Neel Das, SMSC
Paul Stein, Dept of Defense
Priyank Parakh, AMD
Rich Burgess, AMD
Rick Furtner, Consultant
Ron Goodstein, First Shot Logic Simulation and Design
Ronald Kalim, Consultant