Our CoreLink™ Network Interconnect for the AMBA® standard is highly configurable Fabric IP that allows our customers to better meet their performance goals. Synopsys adoption of the CoreLink NIC-301 Network Interconnect into their Platform Architect portfolio is a significant demonstration of their commitment to support ARM’s customers designing at the system-level in SystemC. - Andy Nightingale, Product Manager, Fabric IP, Processor Division, ARM

Product Description

Rapid Configuration of CoreLink Network Interconnect in SystemC
Synopsys and ARM are working together to provide system designers with a SystemC solution for the efficient configuration of CoreLink Network Interconnect based SoC designs.

The joint solution combines the Synopsys SBL-301 SystemC Bus Library for Platform Architect which enables early exploration, and optimization of next-generation SoC architectures in SystemC, and the integration, direct distribution, and support by Synopsys of the ARM CoreLink™ AMBA Designer (ADR-301) tool for CoreLink NIC-301 configuration.

The integrated solution only allows the user to choose legal configurations while performing system-level exploration in Platform Architect, using configuration checks in ADR-301 to validate candidate architectures for SBL-301 SystemC Bus Library. Once an optimal architecture is identified in Platform Architect, the configuration information is saved and re-used by ADR-301 for NIC-301 RTL verification and implementation (RTL generation licenses are available from ARM).

Highlights

Fast and accurate

• Synopsys' SBL-301 SystemC Bus Library fully models the CoreLink NIC-301 Network Interconnect at the transaction-level, for architecture exploration and performance optimization

System-level visibility

• Synopsys Platform Architect and SBL-301 support AMBA protocol-aware transaction tracing and statistical analysis of interconnect performance at the ports and internally across hierarchical transaction paths
• Powerful analysis visualization in Platform Architect enables identification of performance bottlenecks, their root-cause, and the sensitivity that system performance may have to individual or combined parameter settings

Configurability

• Configuration parameters can be set in Platform Architect at run-time, enabling efficient turn-around time for simulation sweeping, data collection, sensitivity analysis, root cause analysis, and the optimization of performance and cost from thousands of candidate architectures

Availability
The joint solution featuring Synopsys Platform Architect, Synopsys SBL-301 SystemC Bus Library, and ARM CoreLink™ AMBA Designer (ADR-301) is available today.
For further information on ARM CoreLink Interconnect visit: http://www.arm.com/products/system-ip/interconnect

For further information on Synopsys Platform Architect and its broad range of available and pre-instrumented ARM architecture models visit: http://www.synopsys.com/PlatformArchitect

Interoperability Description and Customer Benefit

Massive growth in system integration places on-chip communication and interconnect at the center of system performance. The ARM CoreLink Interconnect family is a low risk solution for on-chip communication. Designed and tested with ARM Cortex™ and Mali™ processors, CoreLink interconnect from ARM provides balanced service for both low latency and high bandwidth data streams.

Synopsys Platform Architect is a SystemC TLM standards-based graphical environment for capturing, configuring, simulating, and analyzing the system-level performance of next generation SoC architectures. Its efficient turnaround time, powerful analysis views, and available models make Platform Architect the premier choice for system-level performance analysis and optimization of ARM CoreLink Interconnect based SoCs.

Tell me more about ARM Fabric and Platform Architect.

Flow Diagram